src/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen8_pack.h"
  33 #include "gen9_pack.h"
  34
  35 static void
  36 emit_vertex_input(struct anv_pipeline *pipeline,
  37                   const VkPipelineVertexInputStateCreateInfo *info)
  38 {
  39    const uint32_t num_dwords = 1 + info->vertexAttributeDescriptionCount * 2;
  40    uint32_t *p;
  41
  42    static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
  43
  44    if (info->vertexAttributeDescriptionCount > 0) {
  45       p = anv_batch_emitn(&pipeline->batch, num_dwords,
  46                           GENX(3DSTATE_VERTEX_ELEMENTS));
  47    }
  48
  49    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
  50       const VkVertexInputAttributeDescription *desc =
  51          &info->pVertexAttributeDescriptions[i];
  52       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  53
  54       struct GENX(VERTEX_ELEMENT_STATE) element = {
  55          .VertexBufferIndex = desc->binding,
  56          .Valid = true,
  57          .SourceElementFormat = format->surface_format,
  58          .EdgeFlagEnable = false,
  59          .SourceElementOffset = desc->offset,
  60          .Component0Control = VFCOMP_STORE_SRC,
  61          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  62          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  63          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  64       };
  65       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
  66
  67       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
  68                      .InstancingEnable = pipeline->instancing_enable[desc->binding],
  69                      .VertexElementIndex = i,
  70                      /* Vulkan so far doesn't have an instance divisor, so
  71                       * this is always 1 (ignored if not instancing). */
  72                      .InstanceDataStepRate = 1);
  73    }
  74
  75    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
  76                   .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
  77                   .VertexIDComponentNumber = 2,
  78                   .VertexIDElementOffset = info->vertexBindingDescriptionCount,
  79                   .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
  80                   .InstanceIDComponentNumber = 3,
  81                   .InstanceIDElementOffset = info->vertexBindingDescriptionCount);
  82 }
  83
  84 static void
  85 emit_ia_state(struct anv_pipeline *pipeline,
  86               const VkPipelineInputAssemblyStateCreateInfo *info,
  87               const struct anv_graphics_pipeline_create_info *extra)
  88 {
  89    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
  90                   .PrimitiveTopologyType = pipeline->topology);
  91 }
  92
  93 static void
  94 emit_rs_state(struct anv_pipeline *pipeline,
  95               const VkPipelineRasterizationStateCreateInfo *info,
  96               const struct anv_graphics_pipeline_create_info *extra)
  97 {
  98    static const uint32_t vk_to_gen_cullmode[] = {
  99       [VK_CULL_MODE_NONE]                       = CULLMODE_NONE,
 100       [VK_CULL_MODE_FRONT_BIT]                  = CULLMODE_FRONT,
 101       [VK_CULL_MODE_BACK_BIT]                   = CULLMODE_BACK,
 102       [VK_CULL_MODE_FRONT_AND_BACK]             = CULLMODE_BOTH
 103    };
 104
 105    static const uint32_t vk_to_gen_fillmode[] = {
 106       [VK_POLYGON_MODE_FILL]                    = RASTER_SOLID,
 107       [VK_POLYGON_MODE_LINE]                    = RASTER_WIREFRAME,
 108       [VK_POLYGON_MODE_POINT]                   = RASTER_POINT,
 109    };
 110
 111    static const uint32_t vk_to_gen_front_face[] = {
 112       [VK_FRONT_FACE_COUNTER_CLOCKWISE]         = 1,
 113       [VK_FRONT_FACE_CLOCKWISE]                 = 0
 114    };
 115
 116    struct GENX(3DSTATE_SF) sf = {
 117       GENX(3DSTATE_SF_header),
 118       .ViewportTransformEnable = !(extra && extra->disable_viewport),
 119       .TriangleStripListProvokingVertexSelect = 0,
 120       .LineStripListProvokingVertexSelect = 0,
 121       .TriangleFanProvokingVertexSelect = 0,
 122       .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
 123       .PointWidth = 1.0,
 124    };
 125
 126    /* FINISHME: VkBool32 rasterizerDiscardEnable; */
 127
 128    GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
 129
 130    struct GENX(3DSTATE_RASTER) raster = {
 131       GENX(3DSTATE_RASTER_header),
 132       .FrontWinding = vk_to_gen_front_face[info->frontFace],
 133       .CullMode = vk_to_gen_cullmode[info->cullMode],
 134       .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
 135       .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
 136       .ScissorRectangleEnable = !(extra && extra->disable_scissor),
 137 #if ANV_GEN == 8
 138       .ViewportZClipTestEnable = info->depthClipEnable
 139 #else
 140       /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
 141       .ViewportZFarClipTestEnable = info->depthClipEnable,
 142       .ViewportZNearClipTestEnable = info->depthClipEnable,
 143 #endif
 144    };
 145
 146    GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
 147 }
 148
 149 static void
 150 emit_cb_state(struct anv_pipeline *pipeline,
 151               const VkPipelineColorBlendStateCreateInfo *info,
 152               const VkPipelineMultisampleStateCreateInfo *ms_info)
 153 {
 154    struct anv_device *device = pipeline->device;
 155
 156    static const uint32_t vk_to_gen_logic_op[] = {
 157       [VK_LOGIC_OP_COPY]                        = LOGICOP_COPY,
 158       [VK_LOGIC_OP_CLEAR]                       = LOGICOP_CLEAR,
 159       [VK_LOGIC_OP_AND]                         = LOGICOP_AND,
 160       [VK_LOGIC_OP_AND_REVERSE]                 = LOGICOP_AND_REVERSE,
 161       [VK_LOGIC_OP_AND_INVERTED]                = LOGICOP_AND_INVERTED,
 162       [VK_LOGIC_OP_NO_OP]                       = LOGICOP_NOOP,
 163       [VK_LOGIC_OP_XOR]                         = LOGICOP_XOR,
 164       [VK_LOGIC_OP_OR]                          = LOGICOP_OR,
 165       [VK_LOGIC_OP_NOR]                         = LOGICOP_NOR,
 166       [VK_LOGIC_OP_EQUIVALENT]                  = LOGICOP_EQUIV,
 167       [VK_LOGIC_OP_INVERT]                      = LOGICOP_INVERT,
 168       [VK_LOGIC_OP_OR_REVERSE]                  = LOGICOP_OR_REVERSE,
 169       [VK_LOGIC_OP_COPY_INVERTED]               = LOGICOP_COPY_INVERTED,
 170       [VK_LOGIC_OP_OR_INVERTED]                 = LOGICOP_OR_INVERTED,
 171       [VK_LOGIC_OP_NAND]                        = LOGICOP_NAND,
 172       [VK_LOGIC_OP_SET]                         = LOGICOP_SET,
 173    };
 174
 175    static const uint32_t vk_to_gen_blend[] = {
 176       [VK_BLEND_FACTOR_ZERO]                    = BLENDFACTOR_ZERO,
 177       [VK_BLEND_FACTOR_ONE]                     = BLENDFACTOR_ONE,
 178       [VK_BLEND_FACTOR_SRC_COLOR]               = BLENDFACTOR_SRC_COLOR,
 179       [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]     = BLENDFACTOR_INV_SRC_COLOR,
 180       [VK_BLEND_FACTOR_DST_COLOR]               = BLENDFACTOR_DST_COLOR,
 181       [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]     = BLENDFACTOR_INV_DST_COLOR,
 182       [VK_BLEND_FACTOR_SRC_ALPHA]               = BLENDFACTOR_SRC_ALPHA,
 183       [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]     = BLENDFACTOR_INV_SRC_ALPHA,
 184       [VK_BLEND_FACTOR_DST_ALPHA]               = BLENDFACTOR_DST_ALPHA,
 185       [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]     = BLENDFACTOR_INV_DST_ALPHA,
 186       [VK_BLEND_FACTOR_CONSTANT_COLOR]          = BLENDFACTOR_CONST_COLOR,
 187       [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
 188       [VK_BLEND_FACTOR_CONSTANT_ALPHA]          = BLENDFACTOR_CONST_ALPHA,
 189       [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
 190       [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]      = BLENDFACTOR_SRC_ALPHA_SATURATE,
 191       [VK_BLEND_FACTOR_SRC1_COLOR]              = BLENDFACTOR_SRC1_COLOR,
 192       [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]    = BLENDFACTOR_INV_SRC1_COLOR,
 193       [VK_BLEND_FACTOR_SRC1_ALPHA]              = BLENDFACTOR_SRC1_ALPHA,
 194       [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]    = BLENDFACTOR_INV_SRC1_ALPHA,
 195    };
 196
 197    static const uint32_t vk_to_gen_blend_op[] = {
 198       [VK_BLEND_OP_ADD]                         = BLENDFUNCTION_ADD,
 199       [VK_BLEND_OP_SUBTRACT]                    = BLENDFUNCTION_SUBTRACT,
 200       [VK_BLEND_OP_REVERSE_SUBTRACT]            = BLENDFUNCTION_REVERSE_SUBTRACT,
 201       [VK_BLEND_OP_MIN]                         = BLENDFUNCTION_MIN,
 202       [VK_BLEND_OP_MAX]                         = BLENDFUNCTION_MAX,
 203    };
 204
 205    uint32_t num_dwords = GENX(BLEND_STATE_length);
 206    pipeline->blend_state =
 207       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 208
 209    struct GENX(BLEND_STATE) blend_state = {
 210       .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 211       .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 212    };
 213
 214    for (uint32_t i = 0; i < info->attachmentCount; i++) {
 215       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
 216
 217       if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
 218           a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
 219           a->colorBlendOp != a->alphaBlendOp) {
 220          blend_state.IndependentAlphaBlendEnable = true;
 221       }
 222
 223       blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
 224          .LogicOpEnable = info->logicOpEnable,
 225          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 226          .ColorBufferBlendEnable = a->blendEnable,
 227          .PreBlendSourceOnlyClampEnable = false,
 228          .ColorClampRange = COLORCLAMP_RTFORMAT,
 229          .PreBlendColorClampEnable = true,
 230          .PostBlendColorClampEnable = true,
 231          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 232          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 233          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 234          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 235          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 236          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 237          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 238          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 239          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 240          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 241       };
 242
 243       /* Our hardware applies the blend factor prior to the blend function
 244        * regardless of what function is used.  Technically, this means the
 245        * hardware can do MORE than GL or Vulkan specify.  However, it also
 246        * means that, for MIN and MAX, we have to stomp the blend factor to
 247        * ONE to make it a no-op.
 248        */
 249       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 250           a->colorBlendOp == VK_BLEND_OP_MAX) {
 251          blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
 252          blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
 253       }
 254       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 255           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 256          blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 257          blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 258       }
 259    }
 260
 261    GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
 262
 263    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
 264                   .BlendStatePointer = pipeline->blend_state.offset,
 265                   .BlendStatePointerValid = true);
 266 }
 267
 268 static const uint32_t vk_to_gen_compare_op[] = {
 269    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 270    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 271    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 272    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 273    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 274    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 275    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 276    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 277 };
 278
 279 static const uint32_t vk_to_gen_stencil_op[] = {
 280    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 281    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 282    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 283    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 284    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 285    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 286    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 287    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 288 };
 289
 290 static void
 291 emit_ds_state(struct anv_pipeline *pipeline,
 292               const VkPipelineDepthStencilStateCreateInfo *info)
 293 {
 294    uint32_t *dw = ANV_GEN == 8 ?
 295       pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
 296
 297    if (info == NULL) {
 298       /* We're going to OR this together with the dynamic state.  We need
 299        * to make sure it's initialized to something useful.
 300        */
 301       memset(pipeline->gen8.wm_depth_stencil, 0,
 302              sizeof(pipeline->gen8.wm_depth_stencil));
 303       memset(pipeline->gen9.wm_depth_stencil, 0,
 304              sizeof(pipeline->gen9.wm_depth_stencil));
 305       return;
 306    }
 307
 308    /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
 309
 310    struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 311       .DepthTestEnable = info->depthTestEnable,
 312       .DepthBufferWriteEnable = info->depthWriteEnable,
 313       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 314       .DoubleSidedStencilEnable = true,
 315
 316       .StencilTestEnable = info->stencilTestEnable,
 317       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 318       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 319       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 320       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 321       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 322       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 323       .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
 324       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 325    };
 326
 327    GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
 328 }
 329
 330 VkResult
 331 genX(graphics_pipeline_create)(
 332     VkDevice                                    _device,
 333     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 334     const struct anv_graphics_pipeline_create_info *extra,
 335     const VkAllocationCallbacks*                pAllocator,
 336     VkPipeline*                                 pPipeline)
 337 {
 338    ANV_FROM_HANDLE(anv_device, device, _device);
 339    struct anv_pipeline *pipeline;
 340    VkResult result;
 341    uint32_t offset, length;
 342
 343    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 344
 345    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 346                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 347    if (pipeline == NULL)
 348       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 349
 350    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
 351    if (result != VK_SUCCESS)
 352       return result;
 353
 354    /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
 355     * hard code this to num_attributes - 2. This is because the attributes
 356     * include VUE header and position, which aren't counted as varying
 357     * inputs. */
 358    if (pipeline->vs_simd8 == NO_KERNEL) {
 359       pipeline->wm_prog_data.num_varying_inputs =
 360          pCreateInfo->pVertexInputState->vertexAttributeDescriptionCount - 2;
 361    }
 362
 363    assert(pCreateInfo->pVertexInputState);
 364    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 365    assert(pCreateInfo->pInputAssemblyState);
 366    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
 367    assert(pCreateInfo->pRasterizationState);
 368    emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 369    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 370    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 371                            pCreateInfo->pMultisampleState);
 372
 373    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_STATISTICS),
 374                    .StatisticsEnable = true);
 375    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), .Enable = false);
 376    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), .TEEnable = false);
 377    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), .FunctionEnable = false);
 378    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
 379
 380    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
 381                   .ConstantBufferOffset = 0,
 382                   .ConstantBufferSize = 4);
 383    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS),
 384                   .ConstantBufferOffset = 4,
 385                   .ConstantBufferSize = 4);
 386    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS),
 387                   .ConstantBufferOffset = 8,
 388                   .ConstantBufferSize = 4);
 389
 390    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM_CHROMAKEY),
 391                   .ChromaKeyKillEnable = false);
 392    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
 393
 394    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
 395                   .ClipEnable = true,
 396                   .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
 397                   .MinimumPointWidth = 0.125,
 398                   .MaximumPointWidth = 255.875);
 399
 400    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 401                   .StatisticsEnable = true,
 402                   .LineEndCapAntialiasingRegionWidth = _05pixels,
 403                   .LineAntialiasingRegionWidth = _10pixels,
 404                   .EarlyDepthStencilControl = NORMAL,
 405                   .ForceThreadDispatchEnable = NORMAL,
 406                   .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
 407                   .BarycentricInterpolationMode =
 408                      pipeline->wm_prog_data.barycentric_interp_modes);
 409
 410    uint32_t samples = 1;
 411    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 412    bool enable_sampling = samples > 1 ? true : false;
 413
 414    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
 415                   .PixelPositionOffsetEnable = enable_sampling,
 416                   .PixelLocation = CENTER,
 417                   .NumberofMultisamples = log2_samples);
 418
 419    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
 420                   .SampleMask = 0xffff);
 421
 422    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS),
 423                   .VSURBStartingAddress = pipeline->urb.vs_start,
 424                   .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
 425                   .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
 426
 427    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_GS),
 428                   .GSURBStartingAddress = pipeline->urb.gs_start,
 429                   .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
 430                   .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
 431
 432    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_HS),
 433                   .HSURBStartingAddress = pipeline->urb.vs_start,
 434                   .HSURBEntryAllocationSize = 0,
 435                   .HSNumberofURBEntries = 0);
 436
 437    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_DS),
 438                   .DSURBStartingAddress = pipeline->urb.vs_start,
 439                   .DSURBEntryAllocationSize = 0,
 440                   .DSNumberofURBEntries = 0);
 441
 442    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 443    offset = 1;
 444    length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 445
 446    if (pipeline->gs_vec4 == NO_KERNEL)
 447       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
 448    else
 449       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 450                      .SingleProgramFlow = false,
 451                      .KernelStartPointer = pipeline->gs_vec4,
 452                      .VectorMaskEnable = Dmask,
 453                      .SamplerCount = 0,
 454                      .BindingTableEntryCount = 0,
 455                      .ExpectedVertexCount = pipeline->gs_vertex_count,
 456
 457                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 458                      .PerThreadScratchSpace = ffs(gs_prog_data->base.base.total_scratch / 2048),
 459
 460                      .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 461                      .OutputTopology = gs_prog_data->output_topology,
 462                      .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
 463                      .DispatchGRFStartRegisterForURBData =
 464                         gs_prog_data->base.base.dispatch_grf_start_reg,
 465
 466                      .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
 467                      .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
 468                      .DispatchMode = gs_prog_data->base.dispatch_mode,
 469                      .StatisticsEnable = true,
 470                      .IncludePrimitiveID = gs_prog_data->include_primitive_id,
 471                      .ReorderMode = TRAILING,
 472                      .Enable = true,
 473
 474                      .ControlDataFormat = gs_prog_data->control_data_format,
 475
 476                      .StaticOutput = gs_prog_data->static_vertex_count >= 0,
 477                      .StaticOutputVertexCount =
 478                         gs_prog_data->static_vertex_count >= 0 ?
 479                         gs_prog_data->static_vertex_count : 0,
 480
 481                      /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 482                       * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 483                       * UserClipDistanceCullTestEnableBitmask(v)
 484                       */
 485
 486                      .VertexURBEntryOutputReadOffset = offset,
 487                      .VertexURBEntryOutputLength = length);
 488
 489    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 490    /* Skip the VUE header and position slots */
 491    offset = 1;
 492    length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
 493
 494    if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
 495       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 496                      .FunctionEnable = false,
 497                      /* Even if VS is disabled, SBE still gets the amount of
 498                       * vertex data to read from this field. */
 499                      .VertexURBEntryOutputReadOffset = offset,
 500                      .VertexURBEntryOutputLength = length);
 501    else
 502       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 503                      .KernelStartPointer = pipeline->vs_simd8,
 504                      .SingleVertexDispatch = Multiple,
 505                      .VectorMaskEnable = Dmask,
 506                      .SamplerCount = 0,
 507                      .BindingTableEntryCount =
 508                      vue_prog_data->base.binding_table.size_bytes / 4,
 509                      .ThreadDispatchPriority = Normal,
 510                      .FloatingPointMode = IEEE754,
 511                      .IllegalOpcodeExceptionEnable = false,
 512                      .AccessesUAV = false,
 513                      .SoftwareExceptionEnable = false,
 514
 515                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
 516                      .PerThreadScratchSpace = ffs(vue_prog_data->base.total_scratch / 2048),
 517
 518                      .DispatchGRFStartRegisterForURBData =
 519                      vue_prog_data->base.dispatch_grf_start_reg,
 520                      .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
 521                      .VertexURBEntryReadOffset = 0,
 522
 523                      .MaximumNumberofThreads = device->info.max_vs_threads - 1,
 524                      .StatisticsEnable = false,
 525                      .SIMD8DispatchEnable = true,
 526                      .VertexCacheDisable = false,
 527                      .FunctionEnable = true,
 528
 529                      .VertexURBEntryOutputReadOffset = offset,
 530                      .VertexURBEntryOutputLength = length,
 531                      .UserClipDistanceClipTestEnableBitmask = 0,
 532                      .UserClipDistanceCullTestEnableBitmask = 0);
 533
 534    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 535
 536    /* TODO: We should clean this up.  Among other things, this is mostly
 537     * shared with other gens.
 538     */
 539    const struct brw_vue_map *fs_input_map;
 540    if (pipeline->gs_vec4 == NO_KERNEL)
 541       fs_input_map = &vue_prog_data->vue_map;
 542    else
 543       fs_input_map = &gs_prog_data->base.vue_map;
 544
 545    struct GENX(3DSTATE_SBE_SWIZ) swiz = {
 546       GENX(3DSTATE_SBE_SWIZ_header),
 547    };
 548
 549    int max_source_attr = 0;
 550    for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 551       int input_index = wm_prog_data->urb_setup[attr];
 552
 553       if (input_index < 0)
 554          continue;
 555
 556       /* We have to subtract two slots to accout for the URB entry output
 557        * read offset in the VS and GS stages.
 558        */
 559       int source_attr = fs_input_map->varying_to_slot[attr] - 2;
 560       max_source_attr = MAX2(max_source_attr, source_attr);
 561
 562       if (input_index >= 16)
 563          continue;
 564
 565       swiz.Attribute[input_index].SourceAttribute = source_attr;
 566    }
 567
 568    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
 569                   .AttributeSwizzleEnable = true,
 570                   .ForceVertexURBEntryReadLength = false,
 571                   .ForceVertexURBEntryReadOffset = false,
 572                   .VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2),
 573                   .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 574                   .NumberofSFOutputAttributes =
 575                      wm_prog_data->num_varying_inputs,
 576
 577 #if ANV_GEN >= 9
 578                   .Attribute0ActiveComponentFormat = ACF_XYZW,
 579                   .Attribute1ActiveComponentFormat = ACF_XYZW,
 580                   .Attribute2ActiveComponentFormat = ACF_XYZW,
 581                   .Attribute3ActiveComponentFormat = ACF_XYZW,
 582                   .Attribute4ActiveComponentFormat = ACF_XYZW,
 583                   .Attribute5ActiveComponentFormat = ACF_XYZW,
 584                   .Attribute6ActiveComponentFormat = ACF_XYZW,
 585                   .Attribute7ActiveComponentFormat = ACF_XYZW,
 586                   .Attribute8ActiveComponentFormat = ACF_XYZW,
 587                   .Attribute9ActiveComponentFormat = ACF_XYZW,
 588                   .Attribute10ActiveComponentFormat = ACF_XYZW,
 589                   .Attribute11ActiveComponentFormat = ACF_XYZW,
 590                   .Attribute12ActiveComponentFormat = ACF_XYZW,
 591                   .Attribute13ActiveComponentFormat = ACF_XYZW,
 592                   .Attribute14ActiveComponentFormat = ACF_XYZW,
 593                   .Attribute15ActiveComponentFormat = ACF_XYZW,
 594                   /* wow, much field, very attribute */
 595                   .Attribute16ActiveComponentFormat = ACF_XYZW,
 596                   .Attribute17ActiveComponentFormat = ACF_XYZW,
 597                   .Attribute18ActiveComponentFormat = ACF_XYZW,
 598                   .Attribute19ActiveComponentFormat = ACF_XYZW,
 599                   .Attribute20ActiveComponentFormat = ACF_XYZW,
 600                   .Attribute21ActiveComponentFormat = ACF_XYZW,
 601                   .Attribute22ActiveComponentFormat = ACF_XYZW,
 602                   .Attribute23ActiveComponentFormat = ACF_XYZW,
 603                   .Attribute24ActiveComponentFormat = ACF_XYZW,
 604                   .Attribute25ActiveComponentFormat = ACF_XYZW,
 605                   .Attribute26ActiveComponentFormat = ACF_XYZW,
 606                   .Attribute27ActiveComponentFormat = ACF_XYZW,
 607                   .Attribute28ActiveComponentFormat = ACF_XYZW,
 608                   .Attribute29ActiveComponentFormat = ACF_XYZW,
 609                   .Attribute28ActiveComponentFormat = ACF_XYZW,
 610                   .Attribute29ActiveComponentFormat = ACF_XYZW,
 611                   .Attribute30ActiveComponentFormat = ACF_XYZW,
 612 #endif
 613       );
 614
 615    uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
 616                                         GENX(3DSTATE_SBE_SWIZ_length));
 617    GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
 618
 619    const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
 620    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 621                   .KernelStartPointer0 = pipeline->ps_ksp0,
 622
 623                   .SingleProgramFlow = false,
 624                   .VectorMaskEnable = true,
 625                   .SamplerCount = 1,
 626
 627                   .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 628                   .PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch / 2048),
 629
 630                   .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
 631                   .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
 632                      POSOFFSET_SAMPLE: POSOFFSET_NONE,
 633                   .PushConstantEnable = wm_prog_data->base.nr_params > 0,
 634                   ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
 635                   ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
 636                   ._32PixelDispatchEnable = false,
 637
 638                   .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
 639                   .DispatchGRFStartRegisterForConstantSetupData1 = 0,
 640                   .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
 641
 642                   .KernelStartPointer1 = 0,
 643                   .KernelStartPointer2 = pipeline->ps_ksp2);
 644
 645    bool per_sample_ps = false;
 646    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 647                   .PixelShaderValid = true,
 648                   .PixelShaderKillsPixel = wm_prog_data->uses_kill,
 649                   .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
 650                   .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
 651                   .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
 652                   .PixelShaderIsPerSample = per_sample_ps,
 653 #if ANV_GEN >= 9
 654                   .PixelShaderPullsBary = wm_prog_data->pulls_bary,
 655                   .InputCoverageMaskState = ICMS_NONE
 656 #endif
 657       );
 658
 659    *pPipeline = anv_pipeline_to_handle(pipeline);
 660
 661    return VK_SUCCESS;
 662 }
 663
 664 VkResult genX(compute_pipeline_create)(
 665     VkDevice                                    _device,
 666     const VkComputePipelineCreateInfo*          pCreateInfo,
 667     const VkAllocationCallbacks*                pAllocator,
 668     VkPipeline*                                 pPipeline)
 669 {
 670    ANV_FROM_HANDLE(anv_device, device, _device);
 671    struct anv_pipeline *pipeline;
 672    VkResult result;
 673
 674    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
 675
 676    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 677                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 678    if (pipeline == NULL)
 679       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 680
 681    pipeline->device = device;
 682    pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
 683
 684    pipeline->blend_state.map = NULL;
 685
 686    result = anv_reloc_list_init(&pipeline->batch_relocs,
 687                                 pAllocator ? pAllocator : &device->alloc);
 688    if (result != VK_SUCCESS) {
 689       anv_free2(&device->alloc, pAllocator, pipeline);
 690       return result;
 691    }
 692    pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
 693    pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
 694    pipeline->batch.relocs = &pipeline->batch_relocs;
 695
 696    anv_state_stream_init(&pipeline->program_stream,
 697                          &device->instruction_block_pool);
 698
 699    /* When we free the pipeline, we detect stages based on the NULL status
 700     * of various prog_data pointers.  Make them NULL by default.
 701     */
 702    memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
 703    memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
 704
 705    pipeline->vs_simd8 = NO_KERNEL;
 706    pipeline->vs_vec4 = NO_KERNEL;
 707    pipeline->gs_vec4 = NO_KERNEL;
 708
 709    pipeline->active_stages = 0;
 710    pipeline->total_scratch = 0;
 711
 712    assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
 713    ANV_FROM_HANDLE(anv_shader_module, module,  pCreateInfo->stage.module);
 714    anv_pipeline_compile_cs(pipeline, pCreateInfo, module,
 715                            pCreateInfo->stage.pName);
 716
 717    pipeline->use_repclear = false;
 718
 719    const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
 720
 721    anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE),
 722                   .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_COMPUTE],
 723                   .PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
 724                   .ScratchSpaceBasePointerHigh = 0,
 725                   .StackSize = 0,
 726
 727                   .MaximumNumberofThreads = device->info.max_cs_threads - 1,
 728                   .NumberofURBEntries = 2,
 729                   .ResetGatewayTimer = true,
 730 #if ANV_GEN == 8
 731                   .BypassGatewayControl = true,
 732 #endif
 733                   .URBEntryAllocationSize = 2,
 734                   .CURBEAllocationSize = 0);
 735
 736    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 737    uint32_t group_size = prog_data->local_size[0] *
 738       prog_data->local_size[1] * prog_data->local_size[2];
 739    pipeline->cs_thread_width_max = DIV_ROUND_UP(group_size, prog_data->simd_size);
 740    uint32_t remainder = group_size & (prog_data->simd_size - 1);
 741
 742    if (remainder > 0)
 743       pipeline->cs_right_mask = ~0u >> (32 - remainder);
 744    else
 745       pipeline->cs_right_mask = ~0u >> (32 - prog_data->simd_size);
 746
 747
 748    *pPipeline = anv_pipeline_to_handle(pipeline);
 749
 750    return VK_SUCCESS;
 751 }