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gen7/8/pipeline: s/vb_used/elements in emit_vertex_input
[mesa.git] / src / vulkan / gen8_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
34
35 static void
36 emit_vertex_input(struct anv_pipeline *pipeline,
37 const VkPipelineVertexInputStateCreateInfo *info,
38 const struct anv_graphics_pipeline_create_info *extra)
39 {
40 static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
41
42 uint32_t elements;
43 if (extra && extra->disable_vs) {
44 /* If the VS is disabled, just assume the user knows what they're
45 * doing and apply the layout blindly. This can only come from
46 * meta, so this *should* be safe.
47 */
48 elements = 0;
49 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
50 elements |= (1 << info->pVertexAttributeDescriptions[i].location);
51 } else {
52 /* Pull inputs_read out of the VS prog data */
53 uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
54 assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
55 elements = inputs_read >> VERT_ATTRIB_GENERIC0;
56 }
57
58 const uint32_t num_dwords = 1 + __builtin_popcount(elements) * 2;
59
60 uint32_t *p;
61 if (elements != 0) {
62 p = anv_batch_emitn(&pipeline->batch, num_dwords,
63 GENX(3DSTATE_VERTEX_ELEMENTS));
64 memset(p + 1, 0, (num_dwords - 1) * 4);
65 }
66
67 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
68 const VkVertexInputAttributeDescription *desc =
69 &info->pVertexAttributeDescriptions[i];
70 const struct anv_format *format = anv_format_for_vk_format(desc->format);
71
72 assert(desc->binding < 32);
73
74 if ((elements & (1 << desc->location)) == 0)
75 continue; /* Binding unused */
76
77 uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
78
79 struct GENX(VERTEX_ELEMENT_STATE) element = {
80 .VertexBufferIndex = desc->binding,
81 .Valid = true,
82 .SourceElementFormat = format->surface_format,
83 .EdgeFlagEnable = false,
84 .SourceElementOffset = desc->offset,
85 .Component0Control = VFCOMP_STORE_SRC,
86 .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
87 .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
88 .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
89 };
90 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
91
92 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
93 .InstancingEnable = pipeline->instancing_enable[desc->binding],
94 .VertexElementIndex = slot,
95 /* Vulkan so far doesn't have an instance divisor, so
96 * this is always 1 (ignored if not instancing). */
97 .InstanceDataStepRate = 1);
98 }
99
100 const uint32_t id_slot = __builtin_popcount(elements);
101 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
102 .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
103 .VertexIDComponentNumber = 2,
104 .VertexIDElementOffset = id_slot,
105 .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
106 .InstanceIDComponentNumber = 3,
107 .InstanceIDElementOffset = id_slot);
108 }
109
110 static void
111 emit_ia_state(struct anv_pipeline *pipeline,
112 const VkPipelineInputAssemblyStateCreateInfo *info,
113 const struct anv_graphics_pipeline_create_info *extra)
114 {
115 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
116 .PrimitiveTopologyType = pipeline->topology);
117 }
118
119 static void
120 emit_rs_state(struct anv_pipeline *pipeline,
121 const VkPipelineRasterizationStateCreateInfo *info,
122 const struct anv_graphics_pipeline_create_info *extra)
123 {
124 static const uint32_t vk_to_gen_cullmode[] = {
125 [VK_CULL_MODE_NONE] = CULLMODE_NONE,
126 [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
127 [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
128 [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
129 };
130
131 static const uint32_t vk_to_gen_fillmode[] = {
132 [VK_POLYGON_MODE_FILL] = RASTER_SOLID,
133 [VK_POLYGON_MODE_LINE] = RASTER_WIREFRAME,
134 [VK_POLYGON_MODE_POINT] = RASTER_POINT,
135 };
136
137 static const uint32_t vk_to_gen_front_face[] = {
138 [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
139 [VK_FRONT_FACE_CLOCKWISE] = 0
140 };
141
142 struct GENX(3DSTATE_SF) sf = {
143 GENX(3DSTATE_SF_header),
144 .ViewportTransformEnable = !(extra && extra->disable_viewport),
145 .TriangleStripListProvokingVertexSelect = 0,
146 .LineStripListProvokingVertexSelect = 0,
147 .TriangleFanProvokingVertexSelect = 0,
148 .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
149 .PointWidth = 1.0,
150 };
151
152 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
153
154 GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
155
156 struct GENX(3DSTATE_RASTER) raster = {
157 GENX(3DSTATE_RASTER_header),
158 .FrontWinding = vk_to_gen_front_face[info->frontFace],
159 .CullMode = vk_to_gen_cullmode[info->cullMode],
160 .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
161 .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
162 .ScissorRectangleEnable = !(extra && extra->disable_scissor),
163 #if ANV_GEN == 8
164 .ViewportZClipTestEnable = true,
165 #else
166 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
167 .ViewportZFarClipTestEnable = true,
168 .ViewportZNearClipTestEnable = true,
169 #endif
170 };
171
172 GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
173 }
174
175 static void
176 emit_cb_state(struct anv_pipeline *pipeline,
177 const VkPipelineColorBlendStateCreateInfo *info,
178 const VkPipelineMultisampleStateCreateInfo *ms_info)
179 {
180 struct anv_device *device = pipeline->device;
181
182 static const uint32_t vk_to_gen_logic_op[] = {
183 [VK_LOGIC_OP_COPY] = LOGICOP_COPY,
184 [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
185 [VK_LOGIC_OP_AND] = LOGICOP_AND,
186 [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
187 [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
188 [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
189 [VK_LOGIC_OP_XOR] = LOGICOP_XOR,
190 [VK_LOGIC_OP_OR] = LOGICOP_OR,
191 [VK_LOGIC_OP_NOR] = LOGICOP_NOR,
192 [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
193 [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
194 [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
195 [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
196 [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
197 [VK_LOGIC_OP_NAND] = LOGICOP_NAND,
198 [VK_LOGIC_OP_SET] = LOGICOP_SET,
199 };
200
201 static const uint32_t vk_to_gen_blend[] = {
202 [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
203 [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
204 [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
205 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
206 [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
207 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
208 [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
209 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
210 [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
211 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
212 [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
213 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
214 [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
215 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
216 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
217 [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
218 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
219 [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
220 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
221 };
222
223 static const uint32_t vk_to_gen_blend_op[] = {
224 [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
225 [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
226 [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
227 [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
228 [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
229 };
230
231 uint32_t num_dwords = GENX(BLEND_STATE_length);
232 pipeline->blend_state =
233 anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
234
235 struct GENX(BLEND_STATE) blend_state = {
236 .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
237 .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
238 };
239
240 for (uint32_t i = 0; i < info->attachmentCount; i++) {
241 const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
242
243 if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
244 a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
245 a->colorBlendOp != a->alphaBlendOp) {
246 blend_state.IndependentAlphaBlendEnable = true;
247 }
248
249 blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
250 .LogicOpEnable = info->logicOpEnable,
251 .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
252 .ColorBufferBlendEnable = a->blendEnable,
253 .PreBlendSourceOnlyClampEnable = false,
254 .ColorClampRange = COLORCLAMP_RTFORMAT,
255 .PreBlendColorClampEnable = true,
256 .PostBlendColorClampEnable = true,
257 .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
258 .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
259 .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
260 .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
261 .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
262 .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
263 .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
264 .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
265 .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
266 .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
267 };
268
269 /* Our hardware applies the blend factor prior to the blend function
270 * regardless of what function is used. Technically, this means the
271 * hardware can do MORE than GL or Vulkan specify. However, it also
272 * means that, for MIN and MAX, we have to stomp the blend factor to
273 * ONE to make it a no-op.
274 */
275 if (a->colorBlendOp == VK_BLEND_OP_MIN ||
276 a->colorBlendOp == VK_BLEND_OP_MAX) {
277 blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
278 blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
279 }
280 if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
281 a->alphaBlendOp == VK_BLEND_OP_MAX) {
282 blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
283 blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
284 }
285 }
286
287 GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
288 if (!device->info.has_llc)
289 anv_state_clflush(pipeline->blend_state);
290
291 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
292 .BlendStatePointer = pipeline->blend_state.offset,
293 .BlendStatePointerValid = true);
294 }
295
296 static const uint32_t vk_to_gen_compare_op[] = {
297 [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
298 [VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
299 [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
300 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
301 [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
302 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
303 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
304 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
305 };
306
307 static const uint32_t vk_to_gen_stencil_op[] = {
308 [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
309 [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
310 [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
311 [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
312 [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
313 [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
314 [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
315 [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
316 };
317
318 static void
319 emit_ds_state(struct anv_pipeline *pipeline,
320 const VkPipelineDepthStencilStateCreateInfo *info)
321 {
322 uint32_t *dw = ANV_GEN == 8 ?
323 pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
324
325 if (info == NULL) {
326 /* We're going to OR this together with the dynamic state. We need
327 * to make sure it's initialized to something useful.
328 */
329 memset(pipeline->gen8.wm_depth_stencil, 0,
330 sizeof(pipeline->gen8.wm_depth_stencil));
331 memset(pipeline->gen9.wm_depth_stencil, 0,
332 sizeof(pipeline->gen9.wm_depth_stencil));
333 return;
334 }
335
336 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
337
338 struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
339 .DepthTestEnable = info->depthTestEnable,
340 .DepthBufferWriteEnable = info->depthWriteEnable,
341 .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
342 .DoubleSidedStencilEnable = true,
343
344 .StencilTestEnable = info->stencilTestEnable,
345 .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
346 .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
347 .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
348 .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
349 .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
350 .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
351 .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
352 .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
353 };
354
355 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
356 }
357
358 VkResult
359 genX(graphics_pipeline_create)(
360 VkDevice _device,
361 const VkGraphicsPipelineCreateInfo* pCreateInfo,
362 const struct anv_graphics_pipeline_create_info *extra,
363 const VkAllocationCallbacks* pAllocator,
364 VkPipeline* pPipeline)
365 {
366 ANV_FROM_HANDLE(anv_device, device, _device);
367 struct anv_pipeline *pipeline;
368 VkResult result;
369 uint32_t offset, length;
370
371 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
372
373 pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
374 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
375 if (pipeline == NULL)
376 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
377
378 result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
379 if (result != VK_SUCCESS)
380 return result;
381
382 assert(pCreateInfo->pVertexInputState);
383 emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
384 assert(pCreateInfo->pInputAssemblyState);
385 emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
386 assert(pCreateInfo->pRasterizationState);
387 emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
388 emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
389 emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
390 pCreateInfo->pMultisampleState);
391
392 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_STATISTICS),
393 .StatisticsEnable = true);
394 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), .Enable = false);
395 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), .TEEnable = false);
396 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), .FunctionEnable = false);
397 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
398
399 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
400 .ConstantBufferOffset = 0,
401 .ConstantBufferSize = 4);
402 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS),
403 .ConstantBufferOffset = 4,
404 .ConstantBufferSize = 4);
405 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS),
406 .ConstantBufferOffset = 8,
407 .ConstantBufferSize = 4);
408
409 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM_CHROMAKEY),
410 .ChromaKeyKillEnable = false);
411 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
412
413 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
414 .ClipEnable = true,
415 .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
416 .MinimumPointWidth = 0.125,
417 .MaximumPointWidth = 255.875);
418
419 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
420 .StatisticsEnable = true,
421 .LineEndCapAntialiasingRegionWidth = _05pixels,
422 .LineAntialiasingRegionWidth = _10pixels,
423 .EarlyDepthStencilControl = NORMAL,
424 .ForceThreadDispatchEnable = NORMAL,
425 .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
426 .BarycentricInterpolationMode =
427 pipeline->wm_prog_data.barycentric_interp_modes);
428
429 uint32_t samples = 1;
430 uint32_t log2_samples = __builtin_ffs(samples) - 1;
431 bool enable_sampling = samples > 1 ? true : false;
432
433 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
434 .PixelPositionOffsetEnable = enable_sampling,
435 .PixelLocation = CENTER,
436 .NumberofMultisamples = log2_samples);
437
438 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
439 .SampleMask = 0xffff);
440
441 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS),
442 .VSURBStartingAddress = pipeline->urb.vs_start,
443 .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
444 .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
445
446 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_GS),
447 .GSURBStartingAddress = pipeline->urb.gs_start,
448 .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
449 .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
450
451 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_HS),
452 .HSURBStartingAddress = pipeline->urb.vs_start,
453 .HSURBEntryAllocationSize = 0,
454 .HSNumberofURBEntries = 0);
455
456 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_DS),
457 .DSURBStartingAddress = pipeline->urb.vs_start,
458 .DSURBEntryAllocationSize = 0,
459 .DSNumberofURBEntries = 0);
460
461 const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
462 offset = 1;
463 length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
464
465 if (pipeline->gs_kernel == NO_KERNEL)
466 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
467 else
468 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
469 .SingleProgramFlow = false,
470 .KernelStartPointer = pipeline->gs_kernel,
471 .VectorMaskEnable = Dmask,
472 .SamplerCount = 0,
473 .BindingTableEntryCount = 0,
474 .ExpectedVertexCount = pipeline->gs_vertex_count,
475
476 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
477 .PerThreadScratchSpace = ffs(gs_prog_data->base.base.total_scratch / 2048),
478
479 .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
480 .OutputTopology = gs_prog_data->output_topology,
481 .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
482 .IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
483 .DispatchGRFStartRegisterForURBData =
484 gs_prog_data->base.base.dispatch_grf_start_reg,
485
486 .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
487 .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
488 .DispatchMode = gs_prog_data->base.dispatch_mode,
489 .StatisticsEnable = true,
490 .IncludePrimitiveID = gs_prog_data->include_primitive_id,
491 .ReorderMode = TRAILING,
492 .Enable = true,
493
494 .ControlDataFormat = gs_prog_data->control_data_format,
495
496 .StaticOutput = gs_prog_data->static_vertex_count >= 0,
497 .StaticOutputVertexCount =
498 gs_prog_data->static_vertex_count >= 0 ?
499 gs_prog_data->static_vertex_count : 0,
500
501 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
502 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
503 * UserClipDistanceCullTestEnableBitmask(v)
504 */
505
506 .VertexURBEntryOutputReadOffset = offset,
507 .VertexURBEntryOutputLength = length);
508
509 const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
510 /* Skip the VUE header and position slots */
511 offset = 1;
512 length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
513
514 uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
515 pipeline->vs_vec4;
516
517 if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
518 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
519 .FunctionEnable = false,
520 /* Even if VS is disabled, SBE still gets the amount of
521 * vertex data to read from this field. */
522 .VertexURBEntryOutputReadOffset = offset,
523 .VertexURBEntryOutputLength = length);
524 else
525 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
526 .KernelStartPointer = vs_start,
527 .SingleVertexDispatch = Multiple,
528 .VectorMaskEnable = Dmask,
529 .SamplerCount = 0,
530 .BindingTableEntryCount =
531 vue_prog_data->base.binding_table.size_bytes / 4,
532 .ThreadDispatchPriority = Normal,
533 .FloatingPointMode = IEEE754,
534 .IllegalOpcodeExceptionEnable = false,
535 .AccessesUAV = false,
536 .SoftwareExceptionEnable = false,
537
538 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
539 .PerThreadScratchSpace = ffs(vue_prog_data->base.total_scratch / 2048),
540
541 .DispatchGRFStartRegisterForURBData =
542 vue_prog_data->base.dispatch_grf_start_reg,
543 .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
544 .VertexURBEntryReadOffset = 0,
545
546 .MaximumNumberofThreads = device->info.max_vs_threads - 1,
547 .StatisticsEnable = false,
548 .SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
549 .VertexCacheDisable = false,
550 .FunctionEnable = true,
551
552 .VertexURBEntryOutputReadOffset = offset,
553 .VertexURBEntryOutputLength = length,
554 .UserClipDistanceClipTestEnableBitmask = 0,
555 .UserClipDistanceCullTestEnableBitmask = 0);
556
557 const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
558
559 /* TODO: We should clean this up. Among other things, this is mostly
560 * shared with other gens.
561 */
562 const struct brw_vue_map *fs_input_map;
563 if (pipeline->gs_kernel == NO_KERNEL)
564 fs_input_map = &vue_prog_data->vue_map;
565 else
566 fs_input_map = &gs_prog_data->base.vue_map;
567
568 struct GENX(3DSTATE_SBE_SWIZ) swiz = {
569 GENX(3DSTATE_SBE_SWIZ_header),
570 };
571
572 int max_source_attr = 0;
573 for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
574 int input_index = wm_prog_data->urb_setup[attr];
575
576 if (input_index < 0)
577 continue;
578
579 /* We have to subtract two slots to accout for the URB entry output
580 * read offset in the VS and GS stages.
581 */
582 int source_attr = fs_input_map->varying_to_slot[attr] - 2;
583 max_source_attr = MAX2(max_source_attr, source_attr);
584
585 if (input_index >= 16)
586 continue;
587
588 swiz.Attribute[input_index].SourceAttribute = source_attr;
589 }
590
591 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
592 .AttributeSwizzleEnable = true,
593 .ForceVertexURBEntryReadLength = false,
594 .ForceVertexURBEntryReadOffset = false,
595 .VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2),
596 .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
597 .NumberofSFOutputAttributes =
598 wm_prog_data->num_varying_inputs,
599
600 #if ANV_GEN >= 9
601 .Attribute0ActiveComponentFormat = ACF_XYZW,
602 .Attribute1ActiveComponentFormat = ACF_XYZW,
603 .Attribute2ActiveComponentFormat = ACF_XYZW,
604 .Attribute3ActiveComponentFormat = ACF_XYZW,
605 .Attribute4ActiveComponentFormat = ACF_XYZW,
606 .Attribute5ActiveComponentFormat = ACF_XYZW,
607 .Attribute6ActiveComponentFormat = ACF_XYZW,
608 .Attribute7ActiveComponentFormat = ACF_XYZW,
609 .Attribute8ActiveComponentFormat = ACF_XYZW,
610 .Attribute9ActiveComponentFormat = ACF_XYZW,
611 .Attribute10ActiveComponentFormat = ACF_XYZW,
612 .Attribute11ActiveComponentFormat = ACF_XYZW,
613 .Attribute12ActiveComponentFormat = ACF_XYZW,
614 .Attribute13ActiveComponentFormat = ACF_XYZW,
615 .Attribute14ActiveComponentFormat = ACF_XYZW,
616 .Attribute15ActiveComponentFormat = ACF_XYZW,
617 /* wow, much field, very attribute */
618 .Attribute16ActiveComponentFormat = ACF_XYZW,
619 .Attribute17ActiveComponentFormat = ACF_XYZW,
620 .Attribute18ActiveComponentFormat = ACF_XYZW,
621 .Attribute19ActiveComponentFormat = ACF_XYZW,
622 .Attribute20ActiveComponentFormat = ACF_XYZW,
623 .Attribute21ActiveComponentFormat = ACF_XYZW,
624 .Attribute22ActiveComponentFormat = ACF_XYZW,
625 .Attribute23ActiveComponentFormat = ACF_XYZW,
626 .Attribute24ActiveComponentFormat = ACF_XYZW,
627 .Attribute25ActiveComponentFormat = ACF_XYZW,
628 .Attribute26ActiveComponentFormat = ACF_XYZW,
629 .Attribute27ActiveComponentFormat = ACF_XYZW,
630 .Attribute28ActiveComponentFormat = ACF_XYZW,
631 .Attribute29ActiveComponentFormat = ACF_XYZW,
632 .Attribute28ActiveComponentFormat = ACF_XYZW,
633 .Attribute29ActiveComponentFormat = ACF_XYZW,
634 .Attribute30ActiveComponentFormat = ACF_XYZW,
635 #endif
636 );
637
638 uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
639 GENX(3DSTATE_SBE_SWIZ_length));
640 GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
641
642 const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
643 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
644 .KernelStartPointer0 = pipeline->ps_ksp0,
645
646 .SingleProgramFlow = false,
647 .VectorMaskEnable = true,
648 .SamplerCount = 1,
649
650 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
651 .PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch / 2048),
652
653 .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
654 .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
655 POSOFFSET_SAMPLE: POSOFFSET_NONE,
656 .PushConstantEnable = wm_prog_data->base.nr_params > 0,
657 ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
658 ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
659 ._32PixelDispatchEnable = false,
660
661 .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
662 .DispatchGRFStartRegisterForConstantSetupData1 = 0,
663 .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
664
665 .KernelStartPointer1 = 0,
666 .KernelStartPointer2 = pipeline->ps_ksp2);
667
668 bool per_sample_ps = false;
669 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
670 .PixelShaderValid = true,
671 .PixelShaderKillsPixel = wm_prog_data->uses_kill,
672 .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
673 .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
674 .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
675 .PixelShaderIsPerSample = per_sample_ps,
676 #if ANV_GEN >= 9
677 .PixelShaderPullsBary = wm_prog_data->pulls_bary,
678 .InputCoverageMaskState = ICMS_NONE
679 #endif
680 );
681
682 *pPipeline = anv_pipeline_to_handle(pipeline);
683
684 return VK_SUCCESS;
685 }
686
687 VkResult genX(compute_pipeline_create)(
688 VkDevice _device,
689 const VkComputePipelineCreateInfo* pCreateInfo,
690 const VkAllocationCallbacks* pAllocator,
691 VkPipeline* pPipeline)
692 {
693 ANV_FROM_HANDLE(anv_device, device, _device);
694 struct anv_pipeline *pipeline;
695 VkResult result;
696
697 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
698
699 pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
700 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
701 if (pipeline == NULL)
702 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
703
704 pipeline->device = device;
705 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
706
707 pipeline->blend_state.map = NULL;
708
709 result = anv_reloc_list_init(&pipeline->batch_relocs,
710 pAllocator ? pAllocator : &device->alloc);
711 if (result != VK_SUCCESS) {
712 anv_free2(&device->alloc, pAllocator, pipeline);
713 return result;
714 }
715 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
716 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
717 pipeline->batch.relocs = &pipeline->batch_relocs;
718
719 anv_state_stream_init(&pipeline->program_stream,
720 &device->instruction_block_pool);
721
722 /* When we free the pipeline, we detect stages based on the NULL status
723 * of various prog_data pointers. Make them NULL by default.
724 */
725 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
726 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
727
728 pipeline->vs_simd8 = NO_KERNEL;
729 pipeline->vs_vec4 = NO_KERNEL;
730 pipeline->gs_kernel = NO_KERNEL;
731
732 pipeline->active_stages = 0;
733 pipeline->total_scratch = 0;
734
735 assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
736 ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
737 anv_pipeline_compile_cs(pipeline, pCreateInfo, module,
738 pCreateInfo->stage.pName);
739
740 pipeline->use_repclear = false;
741
742 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
743
744 anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE),
745 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_COMPUTE],
746 .PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
747 .ScratchSpaceBasePointerHigh = 0,
748 .StackSize = 0,
749
750 .MaximumNumberofThreads = device->info.max_cs_threads - 1,
751 .NumberofURBEntries = 2,
752 .ResetGatewayTimer = true,
753 #if ANV_GEN == 8
754 .BypassGatewayControl = true,
755 #endif
756 .URBEntryAllocationSize = 2,
757 .CURBEAllocationSize = 0);
758
759 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
760 uint32_t group_size = prog_data->local_size[0] *
761 prog_data->local_size[1] * prog_data->local_size[2];
762 pipeline->cs_thread_width_max = DIV_ROUND_UP(group_size, prog_data->simd_size);
763 uint32_t remainder = group_size & (prog_data->simd_size - 1);
764
765 if (remainder > 0)
766 pipeline->cs_right_mask = ~0u >> (32 - remainder);
767 else
768 pipeline->cs_right_mask = ~0u >> (32 - prog_data->simd_size);
769
770
771 *pPipeline = anv_pipeline_to_handle(pipeline);
772
773 return VK_SUCCESS;
774 }