2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "gen8_pack.h"
35 emit_vertex_input(struct anv_pipeline
*pipeline
,
36 const VkPipelineVertexInputStateCreateInfo
*info
)
38 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
41 if (info
->attributeCount
> 0) {
42 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
43 GEN8_3DSTATE_VERTEX_ELEMENTS
);
46 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
47 const VkVertexInputAttributeDescription
*desc
=
48 &info
->pVertexAttributeDescriptions
[i
];
49 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
51 struct GEN8_VERTEX_ELEMENT_STATE element
= {
52 .VertexBufferIndex
= desc
->binding
,
54 .SourceElementFormat
= format
->surface_format
,
55 .EdgeFlagEnable
= false,
56 .SourceElementOffset
= desc
->offsetInBytes
,
57 .Component0Control
= VFCOMP_STORE_SRC
,
58 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
59 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
60 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
62 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
64 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
65 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
66 .VertexElementIndex
= i
,
67 /* Vulkan so far doesn't have an instance divisor, so
68 * this is always 1 (ignored if not instancing). */
69 .InstanceDataStepRate
= 1);
72 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
73 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
74 .VertexIDComponentNumber
= 2,
75 .VertexIDElementOffset
= info
->bindingCount
,
76 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
77 .InstanceIDComponentNumber
= 3,
78 .InstanceIDElementOffset
= info
->bindingCount
);
82 emit_ia_state(struct anv_pipeline
*pipeline
,
83 const VkPipelineInputAssemblyStateCreateInfo
*info
,
84 const struct anv_graphics_pipeline_create_info
*extra
)
86 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
87 .PrimitiveTopologyType
= pipeline
->topology
);
91 emit_rs_state(struct anv_pipeline
*pipeline
,
92 const VkPipelineRasterStateCreateInfo
*info
,
93 const struct anv_graphics_pipeline_create_info
*extra
)
95 static const uint32_t vk_to_gen_cullmode
[] = {
96 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
97 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
98 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
99 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
102 static const uint32_t vk_to_gen_fillmode
[] = {
103 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
104 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
105 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
108 static const uint32_t vk_to_gen_front_face
[] = {
109 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
110 [VK_FRONT_FACE_CW
] = Clockwise
113 struct GEN8_3DSTATE_SF sf
= {
114 GEN8_3DSTATE_SF_header
,
115 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
116 .TriangleStripListProvokingVertexSelect
= 0,
117 .LineStripListProvokingVertexSelect
= 0,
118 .TriangleFanProvokingVertexSelect
= 0,
119 .PointWidthSource
= pipeline
->writes_point_size
? Vertex
: State
,
123 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
125 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->gen8
.sf
, &sf
);
127 struct GEN8_3DSTATE_RASTER raster
= {
128 GEN8_3DSTATE_RASTER_header
,
129 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
130 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
131 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
132 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
133 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
134 .ViewportZClipTestEnable
= info
->depthClipEnable
137 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->gen8
.raster
, &raster
);
141 emit_cb_state(struct anv_pipeline
*pipeline
,
142 const VkPipelineColorBlendStateCreateInfo
*info
)
144 struct anv_device
*device
= pipeline
->device
;
146 static const uint32_t vk_to_gen_logic_op
[] = {
147 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
148 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
149 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
150 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
151 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
152 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
153 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
154 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
155 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
156 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
157 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
158 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
159 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
160 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
161 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
162 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
165 static const uint32_t vk_to_gen_blend
[] = {
166 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
167 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
168 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
169 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
170 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
171 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
172 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
173 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
174 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
175 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
176 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
177 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
178 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
179 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
180 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
181 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
182 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
183 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
184 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
187 static const uint32_t vk_to_gen_blend_op
[] = {
188 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
189 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
190 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
191 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
192 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
195 uint32_t num_dwords
= GEN8_BLEND_STATE_length
;
196 pipeline
->blend_state
=
197 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
199 struct GEN8_BLEND_STATE blend_state
= {
200 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
201 .AlphaToOneEnable
= info
->alphaToOneEnable
,
204 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
205 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[i
];
207 blend_state
.Entry
[i
] = (struct GEN8_BLEND_STATE_ENTRY
) {
208 .LogicOpEnable
= info
->logicOpEnable
,
209 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
210 .ColorBufferBlendEnable
= a
->blendEnable
,
211 .PreBlendSourceOnlyClampEnable
= false,
212 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
213 .PreBlendColorClampEnable
= true,
214 .PostBlendColorClampEnable
= true,
215 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
216 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
217 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
218 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
219 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
220 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
221 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
222 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
223 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
224 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
228 GEN8_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
230 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
231 .BlendStatePointer
= pipeline
->blend_state
.offset
,
232 .BlendStatePointerValid
= true);
235 static const uint32_t vk_to_gen_compare_op
[] = {
236 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
237 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
238 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
239 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
240 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
241 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
242 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
243 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
246 static const uint32_t vk_to_gen_stencil_op
[] = {
247 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
248 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
249 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
250 [VK_STENCIL_OP_INC_CLAMP
] = STENCILOP_INCRSAT
,
251 [VK_STENCIL_OP_DEC_CLAMP
] = STENCILOP_DECRSAT
,
252 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
253 [VK_STENCIL_OP_INC_WRAP
] = STENCILOP_INCR
,
254 [VK_STENCIL_OP_DEC_WRAP
] = STENCILOP_DECR
,
258 emit_ds_state(struct anv_pipeline
*pipeline
,
259 const VkPipelineDepthStencilStateCreateInfo
*info
)
262 /* We're going to OR this together with the dynamic state. We need
263 * to make sure it's initialized to something useful.
265 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
266 sizeof(pipeline
->gen8
.wm_depth_stencil
));
270 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
272 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
273 .DepthTestEnable
= info
->depthTestEnable
,
274 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
275 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
276 .DoubleSidedStencilEnable
= true,
278 .StencilTestEnable
= info
->stencilTestEnable
,
279 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
280 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
281 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
282 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
283 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
284 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
285 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
286 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
289 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->gen8
.wm_depth_stencil
, &wm_depth_stencil
);
293 gen8_graphics_pipeline_create(
295 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
296 const struct anv_graphics_pipeline_create_info
*extra
,
297 VkPipeline
* pPipeline
)
299 ANV_FROM_HANDLE(anv_device
, device
, _device
);
300 struct anv_pipeline
*pipeline
;
302 uint32_t offset
, length
;
304 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
306 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
307 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
308 if (pipeline
== NULL
)
309 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
311 result
= anv_pipeline_init(pipeline
, device
, pCreateInfo
, extra
);
312 if (result
!= VK_SUCCESS
)
315 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
316 * hard code this to num_attributes - 2. This is because the attributes
317 * include VUE header and position, which aren't counted as varying
319 if (pipeline
->vs_simd8
== NO_KERNEL
) {
320 pipeline
->wm_prog_data
.num_varying_inputs
=
321 pCreateInfo
->pVertexInputState
->attributeCount
- 2;
324 assert(pCreateInfo
->pVertexInputState
);
325 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
326 assert(pCreateInfo
->pInputAssemblyState
);
327 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
328 assert(pCreateInfo
->pRasterState
);
329 emit_rs_state(pipeline
, pCreateInfo
->pRasterState
, extra
);
330 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
331 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
);
333 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_STATISTICS
,
334 .StatisticsEnable
= true);
335 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_HS
, .Enable
= false);
336 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_TE
, .TEEnable
= false);
337 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_DS
, .FunctionEnable
= false);
338 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
340 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
341 .ConstantBufferOffset
= 0,
342 .ConstantBufferSize
= 4);
343 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
344 .ConstantBufferOffset
= 4,
345 .ConstantBufferSize
= 4);
346 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
347 .ConstantBufferOffset
= 8,
348 .ConstantBufferSize
= 4);
350 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM_CHROMAKEY
,
351 .ChromaKeyKillEnable
= false);
352 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_AA_LINE_PARAMETERS
);
354 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
356 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
357 .MinimumPointWidth
= 0.125,
358 .MaximumPointWidth
= 255.875);
360 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
361 .StatisticsEnable
= true,
362 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
363 .LineAntialiasingRegionWidth
= _10pixels
,
364 .EarlyDepthStencilControl
= NORMAL
,
365 .ForceThreadDispatchEnable
= NORMAL
,
366 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
367 .BarycentricInterpolationMode
=
368 pipeline
->wm_prog_data
.barycentric_interp_modes
);
370 uint32_t samples
= 1;
371 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
372 bool enable_sampling
= samples
> 1 ? true : false;
374 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
375 .PixelPositionOffsetEnable
= enable_sampling
,
376 .PixelLocation
= CENTER
,
377 .NumberofMultisamples
= log2_samples
);
379 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SAMPLE_MASK
,
380 .SampleMask
= 0xffff);
382 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
383 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
384 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
385 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
387 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
388 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
389 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
390 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
392 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
393 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
394 .HSURBEntryAllocationSize
= 0,
395 .HSNumberofURBEntries
= 0);
397 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
398 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
399 .DSURBEntryAllocationSize
= 0,
400 .DSNumberofURBEntries
= 0);
402 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
404 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
406 if (pipeline
->gs_vec4
== NO_KERNEL
)
407 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
409 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
410 .SingleProgramFlow
= false,
411 .KernelStartPointer
= pipeline
->gs_vec4
,
412 .VectorMaskEnable
= Dmask
,
414 .BindingTableEntryCount
= 0,
415 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
417 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
418 .PerThreadScratchSpace
= ffs(gs_prog_data
->base
.base
.total_scratch
/ 2048),
420 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
421 .OutputTopology
= gs_prog_data
->output_topology
,
422 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
423 .DispatchGRFStartRegisterForURBData
=
424 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
426 .MaximumNumberofThreads
= device
->info
.max_gs_threads
/ 2 - 1,
427 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
428 .DispatchMode
= gs_prog_data
->base
.dispatch_mode
,
429 .StatisticsEnable
= true,
430 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
431 .ReorderMode
= TRAILING
,
434 .ControlDataFormat
= gs_prog_data
->control_data_format
,
436 .StaticOutput
= gs_prog_data
->static_vertex_count
>= 0,
437 .StaticOutputVertexCount
=
438 gs_prog_data
->static_vertex_count
>= 0 ?
439 gs_prog_data
->static_vertex_count
: 0,
441 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
442 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
443 * UserClipDistanceCullTestEnableBitmask(v)
446 .VertexURBEntryOutputReadOffset
= offset
,
447 .VertexURBEntryOutputLength
= length
);
449 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
450 /* Skip the VUE header and position slots */
452 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
454 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
455 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
456 .FunctionEnable
= false,
457 /* Even if VS is disabled, SBE still gets the amount of
458 * vertex data to read from this field. */
459 .VertexURBEntryOutputReadOffset
= offset
,
460 .VertexURBEntryOutputLength
= length
);
462 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
463 .KernelStartPointer
= pipeline
->vs_simd8
,
464 .SingleVertexDispatch
= Multiple
,
465 .VectorMaskEnable
= Dmask
,
467 .BindingTableEntryCount
=
468 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
469 .ThreadDispatchPriority
= Normal
,
470 .FloatingPointMode
= IEEE754
,
471 .IllegalOpcodeExceptionEnable
= false,
472 .AccessesUAV
= false,
473 .SoftwareExceptionEnable
= false,
475 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
476 .PerThreadScratchSpace
= ffs(vue_prog_data
->base
.total_scratch
/ 2048),
478 .DispatchGRFStartRegisterForURBData
=
479 vue_prog_data
->base
.dispatch_grf_start_reg
,
480 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
481 .VertexURBEntryReadOffset
= 0,
483 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
484 .StatisticsEnable
= false,
485 .SIMD8DispatchEnable
= true,
486 .VertexCacheDisable
= false,
487 .FunctionEnable
= true,
489 .VertexURBEntryOutputReadOffset
= offset
,
490 .VertexURBEntryOutputLength
= length
,
491 .UserClipDistanceClipTestEnableBitmask
= 0,
492 .UserClipDistanceCullTestEnableBitmask
= 0);
494 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
496 /* TODO: We should clean this up. Among other things, this is mostly
497 * shared with other gens.
499 const struct brw_vue_map
*fs_input_map
;
500 if (pipeline
->gs_vec4
== NO_KERNEL
)
501 fs_input_map
= &vue_prog_data
->vue_map
;
503 fs_input_map
= &gs_prog_data
->base
.vue_map
;
505 struct GEN8_3DSTATE_SBE_SWIZ swiz
= {
506 GEN8_3DSTATE_SBE_SWIZ_header
,
509 int max_source_attr
= 0;
510 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
511 int input_index
= wm_prog_data
->urb_setup
[attr
];
516 /* We have to subtract two slots to accout for the URB entry output
517 * read offset in the VS and GS stages.
519 int source_attr
= fs_input_map
->varying_to_slot
[attr
] - 2;
520 max_source_attr
= MAX2(max_source_attr
, source_attr
);
522 if (input_index
>= 16)
525 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
528 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
529 .AttributeSwizzleEnable
= true,
530 .ForceVertexURBEntryReadLength
= false,
531 .ForceVertexURBEntryReadOffset
= false,
532 .VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2),
533 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
534 .NumberofSFOutputAttributes
=
535 wm_prog_data
->num_varying_inputs
);
537 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
538 GEN8_3DSTATE_SBE_SWIZ_length
);
539 GEN8_3DSTATE_SBE_SWIZ_pack(&pipeline
->batch
, dw
, &swiz
);
541 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
542 .KernelStartPointer0
= pipeline
->ps_ksp0
,
544 .SingleProgramFlow
= false,
545 .VectorMaskEnable
= true,
548 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
549 .PerThreadScratchSpace
= ffs(wm_prog_data
->base
.total_scratch
/ 2048),
551 .MaximumNumberofThreadsPerPSD
= 64 - 2,
552 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
553 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
554 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
555 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
556 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
557 ._32PixelDispatchEnable
= false,
559 .DispatchGRFStartRegisterForConstantSetupData0
= pipeline
->ps_grf_start0
,
560 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
561 .DispatchGRFStartRegisterForConstantSetupData2
= pipeline
->ps_grf_start2
,
563 .KernelStartPointer1
= 0,
564 .KernelStartPointer2
= pipeline
->ps_ksp2
);
566 bool per_sample_ps
= false;
567 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
568 .PixelShaderValid
= true,
569 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
570 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
571 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
572 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
573 .PixelShaderIsPerSample
= per_sample_ps
);
575 *pPipeline
= anv_pipeline_to_handle(pipeline
);
580 VkResult
gen8_compute_pipeline_create(
582 const VkComputePipelineCreateInfo
* pCreateInfo
,
583 VkPipeline
* pPipeline
)
585 ANV_FROM_HANDLE(anv_device
, device
, _device
);
586 struct anv_pipeline
*pipeline
;
589 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
591 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
592 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
593 if (pipeline
== NULL
)
594 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
596 pipeline
->device
= device
;
597 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
599 pipeline
->blend_state
.map
= NULL
;
601 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
602 if (result
!= VK_SUCCESS
) {
603 anv_device_free(device
, pipeline
);
606 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
607 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
608 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
610 anv_state_stream_init(&pipeline
->program_stream
,
611 &device
->instruction_block_pool
);
613 /* When we free the pipeline, we detect stages based on the NULL status
614 * of various prog_data pointers. Make them NULL by default.
616 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
617 memset(pipeline
->scratch_start
, 0, sizeof(pipeline
->scratch_start
));
619 pipeline
->vs_simd8
= NO_KERNEL
;
620 pipeline
->vs_vec4
= NO_KERNEL
;
621 pipeline
->gs_vec4
= NO_KERNEL
;
623 pipeline
->active_stages
= 0;
624 pipeline
->total_scratch
= 0;
626 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE
);
627 ANV_FROM_HANDLE(anv_shader
, shader
, pCreateInfo
->stage
.shader
);
628 anv_pipeline_compile_cs(pipeline
, pCreateInfo
, shader
);
630 pipeline
->use_repclear
= false;
632 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
634 anv_batch_emit(&pipeline
->batch
, GEN8_MEDIA_VFE_STATE
,
635 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_COMPUTE
],
636 .PerThreadScratchSpace
= ffs(cs_prog_data
->base
.total_scratch
/ 2048),
637 .ScratchSpaceBasePointerHigh
= 0,
640 .MaximumNumberofThreads
= device
->info
.max_cs_threads
- 1,
641 .NumberofURBEntries
= 2,
642 .ResetGatewayTimer
= true,
643 .BypassGatewayControl
= true,
644 .URBEntryAllocationSize
= 2,
645 .CURBEAllocationSize
= 0);
647 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
648 uint32_t group_size
= prog_data
->local_size
[0] *
649 prog_data
->local_size
[1] * prog_data
->local_size
[2];
650 pipeline
->cs_thread_width_max
= DIV_ROUND_UP(group_size
, prog_data
->simd_size
);
651 uint32_t remainder
= group_size
& (prog_data
->simd_size
- 1);
654 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
656 pipeline
->cs_right_mask
= ~0u >> (32 - prog_data
->simd_size
);
659 *pPipeline
= anv_pipeline_to_handle(pipeline
);