2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
33 emit_vertex_input(struct anv_pipeline
*pipeline
,
34 const VkPipelineVertexInputStateCreateInfo
*info
)
36 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
39 if (info
->attributeCount
> 0) {
40 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
41 GEN8_3DSTATE_VERTEX_ELEMENTS
);
44 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
45 const VkVertexInputAttributeDescription
*desc
=
46 &info
->pVertexAttributeDescriptions
[i
];
47 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
49 struct GEN8_VERTEX_ELEMENT_STATE element
= {
50 .VertexBufferIndex
= desc
->binding
,
52 .SourceElementFormat
= format
->surface_format
,
53 .EdgeFlagEnable
= false,
54 .SourceElementOffset
= desc
->offsetInBytes
,
55 .Component0Control
= VFCOMP_STORE_SRC
,
56 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
57 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
58 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
60 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
62 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
63 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
64 .VertexElementIndex
= i
,
65 /* Vulkan so far doesn't have an instance divisor, so
66 * this is always 1 (ignored if not instancing). */
67 .InstanceDataStepRate
= 1);
70 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
71 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
72 .VertexIDComponentNumber
= 2,
73 .VertexIDElementOffset
= info
->bindingCount
,
74 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
75 .InstanceIDComponentNumber
= 3,
76 .InstanceIDElementOffset
= info
->bindingCount
);
80 emit_ia_state(struct anv_pipeline
*pipeline
,
81 const VkPipelineInputAssemblyStateCreateInfo
*info
,
82 const struct anv_graphics_pipeline_create_info
*extra
)
84 struct GEN8_3DSTATE_VF vf
= {
85 GEN8_3DSTATE_VF_header
,
86 .IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
88 GEN8_3DSTATE_VF_pack(NULL
, pipeline
->gen8
.vf
, &vf
);
90 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
91 .PrimitiveTopologyType
= pipeline
->topology
);
95 emit_rs_state(struct anv_pipeline
*pipeline
,
96 const VkPipelineRasterStateCreateInfo
*info
,
97 const struct anv_graphics_pipeline_create_info
*extra
)
99 static const uint32_t vk_to_gen_cullmode
[] = {
100 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
101 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
102 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
103 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
106 static const uint32_t vk_to_gen_fillmode
[] = {
107 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
108 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
109 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
112 static const uint32_t vk_to_gen_front_face
[] = {
113 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
114 [VK_FRONT_FACE_CW
] = Clockwise
117 struct GEN8_3DSTATE_SF sf
= {
118 GEN8_3DSTATE_SF_header
,
119 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
120 .TriangleStripListProvokingVertexSelect
= 0,
121 .LineStripListProvokingVertexSelect
= 0,
122 .TriangleFanProvokingVertexSelect
= 0,
123 .PointWidthSource
= pipeline
->writes_point_size
? Vertex
: State
,
127 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
129 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->gen8
.sf
, &sf
);
131 struct GEN8_3DSTATE_RASTER raster
= {
132 GEN8_3DSTATE_RASTER_header
,
133 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
134 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
135 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
136 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
137 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
138 .ViewportZClipTestEnable
= info
->depthClipEnable
141 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->gen8
.raster
, &raster
);
145 emit_cb_state(struct anv_pipeline
*pipeline
,
146 const VkPipelineColorBlendStateCreateInfo
*info
)
148 struct anv_device
*device
= pipeline
->device
;
150 static const uint32_t vk_to_gen_logic_op
[] = {
151 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
152 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
153 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
154 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
155 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
156 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
157 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
158 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
159 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
160 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
161 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
162 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
163 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
164 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
165 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
166 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
169 static const uint32_t vk_to_gen_blend
[] = {
170 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
171 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
172 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
173 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
174 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
175 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
176 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
177 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
178 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
179 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
180 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
181 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
182 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
183 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
184 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
185 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
186 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
187 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
188 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
191 static const uint32_t vk_to_gen_blend_op
[] = {
192 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
193 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
194 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
195 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
196 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
199 uint32_t num_dwords
= GEN8_BLEND_STATE_length
;
200 pipeline
->blend_state
=
201 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
203 struct GEN8_BLEND_STATE blend_state
= {
204 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
207 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
208 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[i
];
210 blend_state
.Entry
[i
] = (struct GEN8_BLEND_STATE_ENTRY
) {
211 .LogicOpEnable
= info
->logicOpEnable
,
212 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
213 .ColorBufferBlendEnable
= a
->blendEnable
,
214 .PreBlendSourceOnlyClampEnable
= false,
215 .PreBlendColorClampEnable
= false,
216 .PostBlendColorClampEnable
= false,
217 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
218 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
219 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
220 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
221 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
222 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
223 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
224 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
225 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
226 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
230 GEN8_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
232 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
233 .BlendStatePointer
= pipeline
->blend_state
.offset
,
234 .BlendStatePointerValid
= true);
237 static const uint32_t vk_to_gen_compare_op
[] = {
238 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
239 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
240 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
241 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
242 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
243 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
244 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
245 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
248 static const uint32_t vk_to_gen_stencil_op
[] = {
249 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
250 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
251 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
252 [VK_STENCIL_OP_INC_CLAMP
] = STENCILOP_INCRSAT
,
253 [VK_STENCIL_OP_DEC_CLAMP
] = STENCILOP_DECRSAT
,
254 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
255 [VK_STENCIL_OP_INC_WRAP
] = STENCILOP_INCR
,
256 [VK_STENCIL_OP_DEC_WRAP
] = STENCILOP_DECR
,
260 emit_ds_state(struct anv_pipeline
*pipeline
,
261 const VkPipelineDepthStencilStateCreateInfo
*info
)
264 /* We're going to OR this together with the dynamic state. We need
265 * to make sure it's initialized to something useful.
267 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
268 sizeof(pipeline
->gen8
.wm_depth_stencil
));
272 /* VkBool32 depthBoundsEnable; // optional (depth_bounds_test) */
274 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
275 .DepthTestEnable
= info
->depthTestEnable
,
276 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
277 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
278 .DoubleSidedStencilEnable
= true,
280 .StencilTestEnable
= info
->stencilTestEnable
,
281 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
282 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
283 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
284 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
285 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
286 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
287 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
288 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
291 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->gen8
.wm_depth_stencil
, &wm_depth_stencil
);
295 gen8_graphics_pipeline_create(
297 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
298 const struct anv_graphics_pipeline_create_info
*extra
,
299 VkPipeline
* pPipeline
)
301 ANV_FROM_HANDLE(anv_device
, device
, _device
);
302 struct anv_pipeline
*pipeline
;
304 uint32_t offset
, length
;
306 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
308 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
309 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
310 if (pipeline
== NULL
)
311 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
313 result
= anv_pipeline_init(pipeline
, device
, pCreateInfo
, extra
);
314 if (result
!= VK_SUCCESS
)
317 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
318 * hard code this to num_attributes - 2. This is because the attributes
319 * include VUE header and position, which aren't counted as varying
321 if (pipeline
->vs_simd8
== NO_KERNEL
) {
322 pipeline
->wm_prog_data
.num_varying_inputs
=
323 pCreateInfo
->pVertexInputState
->attributeCount
- 2;
326 assert(pCreateInfo
->pVertexInputState
);
327 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
328 assert(pCreateInfo
->pInputAssemblyState
);
329 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
330 assert(pCreateInfo
->pRasterState
);
331 emit_rs_state(pipeline
, pCreateInfo
->pRasterState
, extra
);
332 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
333 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
);
335 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_STATISTICS
,
336 .StatisticsEnable
= true);
337 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_HS
, .Enable
= false);
338 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_TE
, .TEEnable
= false);
339 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_DS
, .FunctionEnable
= false);
340 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
342 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
343 .ConstantBufferOffset
= 0,
344 .ConstantBufferSize
= 4);
345 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
346 .ConstantBufferOffset
= 4,
347 .ConstantBufferSize
= 4);
348 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
349 .ConstantBufferOffset
= 8,
350 .ConstantBufferSize
= 4);
352 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM_CHROMAKEY
,
353 .ChromaKeyKillEnable
= false);
354 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE_SWIZ
);
355 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_AA_LINE_PARAMETERS
);
357 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
359 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
360 .MinimumPointWidth
= 0.125,
361 .MaximumPointWidth
= 255.875);
363 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
364 .StatisticsEnable
= true,
365 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
366 .LineAntialiasingRegionWidth
= _10pixels
,
367 .EarlyDepthStencilControl
= NORMAL
,
368 .ForceThreadDispatchEnable
= NORMAL
,
369 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
370 .BarycentricInterpolationMode
=
371 pipeline
->wm_prog_data
.barycentric_interp_modes
);
373 uint32_t samples
= 1;
374 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
375 bool enable_sampling
= samples
> 1 ? true : false;
377 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
378 .PixelPositionOffsetEnable
= enable_sampling
,
379 .PixelLocation
= CENTER
,
380 .NumberofMultisamples
= log2_samples
);
382 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SAMPLE_MASK
,
383 .SampleMask
= 0xffff);
385 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
386 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
387 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
388 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
390 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
391 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
392 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
393 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
395 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
396 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
397 .HSURBEntryAllocationSize
= 0,
398 .HSNumberofURBEntries
= 0);
400 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
401 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
402 .DSURBEntryAllocationSize
= 0,
403 .DSNumberofURBEntries
= 0);
405 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
407 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
409 if (pipeline
->gs_vec4
== NO_KERNEL
)
410 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
412 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
413 .SingleProgramFlow
= false,
414 .KernelStartPointer
= pipeline
->gs_vec4
,
415 .VectorMaskEnable
= Vmask
,
417 .BindingTableEntryCount
= 0,
418 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
420 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
421 .PerThreadScratchSpace
= ffs(gs_prog_data
->base
.base
.total_scratch
/ 2048),
423 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
424 .OutputTopology
= gs_prog_data
->output_topology
,
425 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
426 .DispatchGRFStartRegisterForURBData
=
427 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
429 .MaximumNumberofThreads
= device
->info
.max_gs_threads
,
430 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
431 //pipeline->gs_prog_data.dispatch_mode |
432 .StatisticsEnable
= true,
433 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
434 .ReorderMode
= TRAILING
,
437 .ControlDataFormat
= gs_prog_data
->control_data_format
,
439 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
440 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
441 * UserClipDistanceCullTestEnableBitmask(v)
444 .VertexURBEntryOutputReadOffset
= offset
,
445 .VertexURBEntryOutputLength
= length
);
447 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
448 /* Skip the VUE header and position slots */
450 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
452 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
453 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
454 .FunctionEnable
= false,
455 /* Even if VS is disabled, SBE still gets the amount of
456 * vertex data to read from this field. */
457 .VertexURBEntryOutputReadOffset
= offset
,
458 .VertexURBEntryOutputLength
= length
);
460 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
461 .KernelStartPointer
= pipeline
->vs_simd8
,
462 .SingleVertexDispatch
= Multiple
,
463 .VectorMaskEnable
= Dmask
,
465 .BindingTableEntryCount
=
466 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
467 .ThreadDispatchPriority
= Normal
,
468 .FloatingPointMode
= IEEE754
,
469 .IllegalOpcodeExceptionEnable
= false,
470 .AccessesUAV
= false,
471 .SoftwareExceptionEnable
= false,
473 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
474 .PerThreadScratchSpace
= ffs(vue_prog_data
->base
.total_scratch
/ 2048),
476 .DispatchGRFStartRegisterForURBData
=
477 vue_prog_data
->base
.dispatch_grf_start_reg
,
478 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
479 .VertexURBEntryReadOffset
= 0,
481 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
482 .StatisticsEnable
= false,
483 .SIMD8DispatchEnable
= true,
484 .VertexCacheDisable
= false,
485 .FunctionEnable
= true,
487 .VertexURBEntryOutputReadOffset
= offset
,
488 .VertexURBEntryOutputLength
= length
,
489 .UserClipDistanceClipTestEnableBitmask
= 0,
490 .UserClipDistanceCullTestEnableBitmask
= 0);
492 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
494 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
495 .ForceVertexURBEntryReadLength
= false,
496 .ForceVertexURBEntryReadOffset
= false,
497 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
498 .NumberofSFOutputAttributes
=
499 wm_prog_data
->num_varying_inputs
);
501 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
502 .KernelStartPointer0
= pipeline
->ps_ksp0
,
504 .SingleProgramFlow
= false,
505 .VectorMaskEnable
= true,
508 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
509 .PerThreadScratchSpace
= ffs(wm_prog_data
->base
.total_scratch
/ 2048),
511 .MaximumNumberofThreadsPerPSD
= 64 - 2,
512 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
513 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
514 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
515 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
516 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
517 ._32PixelDispatchEnable
= false,
519 .DispatchGRFStartRegisterForConstantSetupData0
= pipeline
->ps_grf_start0
,
520 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
521 .DispatchGRFStartRegisterForConstantSetupData2
= pipeline
->ps_grf_start2
,
523 .KernelStartPointer1
= 0,
524 .KernelStartPointer2
= pipeline
->ps_ksp2
);
526 bool per_sample_ps
= false;
527 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
528 .PixelShaderValid
= true,
529 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
530 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
531 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
532 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
533 .PixelShaderIsPerSample
= per_sample_ps
);
535 *pPipeline
= anv_pipeline_to_handle(pipeline
);
540 VkResult
gen8_compute_pipeline_create(
542 const VkComputePipelineCreateInfo
* pCreateInfo
,
543 VkPipeline
* pPipeline
)
545 ANV_FROM_HANDLE(anv_device
, device
, _device
);
546 struct anv_pipeline
*pipeline
;
549 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
551 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
552 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
553 if (pipeline
== NULL
)
554 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
556 pipeline
->device
= device
;
557 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
559 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
560 if (result
!= VK_SUCCESS
) {
561 anv_device_free(device
, pipeline
);
564 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
565 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
566 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
568 anv_state_stream_init(&pipeline
->program_stream
,
569 &device
->instruction_block_pool
);
571 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
573 pipeline
->shaders
[VK_SHADER_STAGE_COMPUTE
] =
574 anv_shader_from_handle(pCreateInfo
->cs
.shader
);
576 pipeline
->use_repclear
= false;
578 anv_compiler_run(device
->compiler
, pipeline
);
580 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
582 anv_batch_emit(&pipeline
->batch
, GEN8_MEDIA_VFE_STATE
,
583 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
584 .PerThreadScratchSpace
= ffs(cs_prog_data
->base
.total_scratch
/ 2048),
585 .ScratchSpaceBasePointerHigh
= 0,
588 .MaximumNumberofThreads
= device
->info
.max_cs_threads
- 1,
589 .NumberofURBEntries
= 2,
590 .ResetGatewayTimer
= true,
591 .BypassGatewayControl
= true,
592 .URBEntryAllocationSize
= 2,
593 .CURBEAllocationSize
= 0);
595 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
596 uint32_t group_size
= prog_data
->local_size
[0] *
597 prog_data
->local_size
[1] * prog_data
->local_size
[2];
598 pipeline
->cs_thread_width_max
= DIV_ROUND_UP(group_size
, prog_data
->simd_size
);
599 uint32_t remainder
= group_size
& (prog_data
->simd_size
- 1);
602 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
604 pipeline
->cs_right_mask
= ~0u >> (32 - prog_data
->simd_size
);
607 *pPipeline
= anv_pipeline_to_handle(pipeline
);