src/vulkan/gen8_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen8_pack.h"
  33 #include "gen9_pack.h"
  34
  35 #include "genX_state_util.h"
  36
  37 void
  38 genX(fill_buffer_surface_state)(void *state, enum isl_format format,
  39                                 uint32_t offset, uint32_t range, uint32_t stride)
  40 {
  41    uint32_t num_elements = range / stride;
  42
  43    struct GENX(RENDER_SURFACE_STATE) surface_state = {
  44       .SurfaceType = SURFTYPE_BUFFER,
  45       .SurfaceArray = false,
  46       .SurfaceFormat = format,
  47       .SurfaceVerticalAlignment = VALIGN4,
  48       .SurfaceHorizontalAlignment = HALIGN4,
  49       .TileMode = LINEAR,
  50       .SamplerL2BypassModeDisable = true,
  51       .RenderCacheReadWriteMode = WriteOnlyCache,
  52       .MemoryObjectControlState = GENX(MOCS),
  53       .Height = ((num_elements - 1) >> 7) & 0x3fff,
  54       .Width = (num_elements - 1) & 0x7f,
  55       .Depth = ((num_elements - 1) >> 21) & 0x3f,
  56       .SurfacePitch = stride - 1,
  57       .NumberofMultisamples = MULTISAMPLECOUNT_1,
  58       .ShaderChannelSelectRed = SCS_RED,
  59       .ShaderChannelSelectGreen = SCS_GREEN,
  60       .ShaderChannelSelectBlue = SCS_BLUE,
  61       .ShaderChannelSelectAlpha = SCS_ALPHA,
  62       /* FIXME: We assume that the image must be bound at this time. */
  63       .SurfaceBaseAddress = { NULL, offset },
  64    };
  65
  66    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
  67 }
  68
  69 static const uint8_t anv_halign[] = {
  70     [4] = HALIGN4,
  71     [8] = HALIGN8,
  72     [16] = HALIGN16,
  73 };
  74
  75 static const uint8_t anv_valign[] = {
  76     [4] = VALIGN4,
  77     [8] = VALIGN8,
  78     [16] = VALIGN16,
  79 };
  80
  81 static struct anv_state
  82 alloc_surface_state(struct anv_device *device,
  83                     struct anv_cmd_buffer *cmd_buffer)
  84 {
  85       if (cmd_buffer) {
  86          return anv_cmd_buffer_alloc_surface_state(cmd_buffer);
  87       } else {
  88          return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
  89       }
  90 }
  91
  92 /**
  93  * Get the values to pack into RENDER_SUFFACE_STATE.SurfaceHorizontalAlignment
  94  * and SurfaceVerticalAlignment.
  95  */
  96 static void
  97 get_halign_valign(const struct isl_surf *surf, uint32_t *halign, uint32_t *valign)
  98 {
  99    #if ANV_GENx10 >= 90
 100       if (isl_tiling_is_std_y(surf->tiling) ||
 101           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 102          /* The hardware ignores the alignment values. Anyway, the surface's
 103           * true alignment is likely outside the enum range of HALIGN* and
 104           * VALIGN*.
 105           */
 106          *halign = 0;
 107          *valign = 0;
 108       } else {
 109          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 110           * of surface elements (not pixels nor samples). For compressed formats,
 111           * a "surface element" is defined as a compression block.  For example,
 112           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 113           * format (ETC2 has a block height of 4), then the vertical alignment is
 114           * 4 compression blocks or, equivalently, 16 pixels.
 115           */
 116          struct isl_extent3d image_align_el
 117             = isl_surf_get_image_alignment_el(surf);
 118
 119          *halign = anv_halign[image_align_el.width];
 120          *valign = anv_valign[image_align_el.height];
 121       }
 122    #else
 123       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 124        * units of surface samples.  For example, if SurfaceVerticalAlignment
 125        * is VALIGN_4 and the surface is singlesampled, then for any surface
 126        * format (compressed or not) the vertical alignment is
 127        * 4 pixels.
 128        */
 129       struct isl_extent3d image_align_sa
 130          = isl_surf_get_image_alignment_sa(surf);
 131
 132       *halign = anv_halign[image_align_sa.width];
 133       *valign = anv_valign[image_align_sa.height];
 134    #endif
 135 }
 136
 137 static uint32_t
 138 get_qpitch(const struct isl_surf *surf)
 139 {
 140    switch (surf->dim) {
 141    default:
 142       unreachable(!"bad isl_surf_dim");
 143    case ISL_SURF_DIM_1D:
 144       #if ANV_GENx10 >= 90
 145          /* QPitch is usually expressed as rows of surface elements (where
 146           * a surface element is an compression block or a single surface
 147           * sample). Skylake 1D is an outlier.
 148           *
 149           * From the Skylake BSpec >> Memory Views >> Common Surface
 150           * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 151           *
 152           *    Surface QPitch specifies the distance in pixels between array
 153           *    slices.
 154           */
 155          return isl_surf_get_array_pitch_el(surf);
 156       #else
 157          return isl_surf_get_array_pitch_el_rows(surf);
 158       #endif
 159    case ISL_SURF_DIM_2D:
 160    case ISL_SURF_DIM_3D:
 161       return isl_surf_get_array_pitch_el_rows(surf);
 162    }
 163 }
 164
 165 void
 166 genX(image_view_init)(struct anv_image_view *iview,
 167                       struct anv_device *device,
 168                       const VkImageViewCreateInfo* pCreateInfo,
 169                       struct anv_cmd_buffer *cmd_buffer)
 170 {
 171    ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
 172
 173    const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
 174
 175    struct anv_surface *surface =
 176       anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
 177
 178    uint32_t depth = 1; /* RENDER_SURFACE_STATE::Depth */
 179    uint32_t rt_view_extent = 1; /* RENDER_SURFACE_STATE::RenderTargetViewExtent */
 180
 181    switch (image->type) {
 182    case VK_IMAGE_TYPE_1D:
 183    case VK_IMAGE_TYPE_2D:
 184       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 185        *
 186        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 187        *    by one for each increase from zero of Minimum Array Element. For
 188        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 189        *    the range of this field is reduced to [0,1023].
 190        */
 191       depth = range->layerCount;
 192
 193       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 194        *
 195        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 196        *    This field must be set to the same value as the Depth field.
 197        */
 198       rt_view_extent = depth;
 199       break;
 200    case VK_IMAGE_TYPE_3D:
 201       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 202        *
 203        *    If the volume texture is MIP-mapped, this field specifies the
 204        *    depth of the base MIP level.
 205        */
 206       depth = image->extent.depth;
 207
 208       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 209        *
 210        *    For Render Target and Typed Dataport 3D Surfaces: This field
 211        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 212        *    the LOD currently being rendered to.
 213        */
 214       rt_view_extent = iview->extent.depth;
 215       break;
 216    default:
 217       unreachable(!"bad VkImageType");
 218    }
 219
 220    static const uint8_t isl_to_gen_tiling[] = {
 221       [ISL_TILING_LINEAR]  = LINEAR,
 222       [ISL_TILING_X]       = XMAJOR,
 223       [ISL_TILING_Y0]      = YMAJOR,
 224       [ISL_TILING_Yf]      = YMAJOR,
 225       [ISL_TILING_Ys]      = YMAJOR,
 226       [ISL_TILING_W]       = WMAJOR,
 227    };
 228
 229    uint32_t halign, valign;
 230    get_halign_valign(&surface->isl, &halign, &valign);
 231
 232    struct GENX(RENDER_SURFACE_STATE) surface_state = {
 233       .SurfaceType = anv_surftype(image, pCreateInfo->viewType, false),
 234       .SurfaceArray = image->array_size > 1,
 235       .SurfaceFormat = iview->format,
 236       .SurfaceVerticalAlignment = valign,
 237       .SurfaceHorizontalAlignment = halign,
 238       .TileMode = isl_to_gen_tiling[surface->isl.tiling],
 239       .VerticalLineStride = 0,
 240       .VerticalLineStrideOffset = 0,
 241       .SamplerL2BypassModeDisable = true,
 242       .RenderCacheReadWriteMode = WriteOnlyCache,
 243       .MemoryObjectControlState = GENX(MOCS),
 244
 245       /* The driver sets BaseMipLevel in SAMPLER_STATE, not here in
 246        * RENDER_SURFACE_STATE. The Broadwell PRM says "it is illegal to have
 247        * both Base Mip Level fields nonzero".
 248        */
 249       .BaseMipLevel = 0.0,
 250
 251       .SurfaceQPitch = get_qpitch(&surface->isl) >> 2,
 252       .Height = image->extent.height - 1,
 253       .Width = image->extent.width - 1,
 254       .Depth = depth - 1,
 255       .SurfacePitch = surface->isl.row_pitch - 1,
 256       .RenderTargetViewExtent = rt_view_extent - 1,
 257       .MinimumArrayElement = range->baseArrayLayer,
 258       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 259       .XOffset = 0,
 260       .YOffset = 0,
 261
 262       .MIPCountLOD = 0, /* TEMPLATE */
 263       .SurfaceMinLOD = 0, /* TEMPLATE */
 264
 265       .AuxiliarySurfaceMode = AUX_NONE,
 266       .RedClearColor = 0,
 267       .GreenClearColor = 0,
 268       .BlueClearColor = 0,
 269       .AlphaClearColor = 0,
 270       .ShaderChannelSelectRed = vk_to_gen_swizzle(pCreateInfo->components.r,
 271                                                   VK_COMPONENT_SWIZZLE_R),
 272       .ShaderChannelSelectGreen = vk_to_gen_swizzle(pCreateInfo->components.g,
 273                                                     VK_COMPONENT_SWIZZLE_G),
 274       .ShaderChannelSelectBlue = vk_to_gen_swizzle(pCreateInfo->components.b,
 275                                                    VK_COMPONENT_SWIZZLE_B),
 276       .ShaderChannelSelectAlpha = vk_to_gen_swizzle(pCreateInfo->components.a,
 277                                                     VK_COMPONENT_SWIZZLE_A),
 278       .ResourceMinLOD = 0.0,
 279       .SurfaceBaseAddress = { NULL, iview->offset },
 280    };
 281
 282    if (image->needs_nonrt_surface_state) {
 283       iview->nonrt_surface_state =
 284          alloc_surface_state(device, cmd_buffer);
 285
 286       /* For non render target surfaces, the hardware interprets field
 287        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 288        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 289        */
 290       surface_state.SurfaceMinLOD = range->baseMipLevel;
 291       surface_state.MIPCountLOD = MAX2(range->levelCount, 1) - 1;
 292
 293       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map,
 294                                       &surface_state);
 295       if (!device->info.has_llc)
 296          anv_state_clflush(iview->nonrt_surface_state);
 297    }
 298
 299    if (image->needs_color_rt_surface_state) {
 300       iview->color_rt_surface_state =
 301          alloc_surface_state(device, cmd_buffer);
 302
 303       /* For render target surfaces, the hardware interprets field
 304        * MIPCount/LOD as LOD. The Broadwell PRM says:
 305        *
 306        *    MIPCountLOD defines the LOD that will be rendered into.
 307        *    SurfaceMinLOD is ignored.
 308        */
 309       surface_state.MIPCountLOD = range->baseMipLevel;
 310       surface_state.SurfaceMinLOD = 0;
 311
 312       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map,
 313                                       &surface_state);
 314       if (!device->info.has_llc)
 315          anv_state_clflush(iview->color_rt_surface_state);
 316    }
 317
 318    if (image->needs_storage_surface_state) {
 319       iview->storage_surface_state =
 320          alloc_surface_state(device, cmd_buffer);
 321
 322       surface_state.SurfaceType =
 323          anv_surftype(image, pCreateInfo->viewType, true),
 324
 325       surface_state.SurfaceFormat =
 326          isl_lower_storage_image_format(&device->isl_dev, iview->format);
 327
 328       surface_state.SurfaceMinLOD = range->baseMipLevel;
 329       surface_state.MIPCountLOD = MAX2(range->levelCount, 1) - 1;
 330
 331       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->storage_surface_state.map,
 332                                       &surface_state);
 333    }
 334 }
 335
 336 VkResult genX(CreateSampler)(
 337     VkDevice                                    _device,
 338     const VkSamplerCreateInfo*                  pCreateInfo,
 339     const VkAllocationCallbacks*                pAllocator,
 340     VkSampler*                                  pSampler)
 341 {
 342    ANV_FROM_HANDLE(anv_device, device, _device);
 343    struct anv_sampler *sampler;
 344    uint32_t mag_filter, min_filter, max_anisotropy;
 345
 346    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 347
 348    sampler = anv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
 349                         VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 350    if (!sampler)
 351       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 352
 353    if (pCreateInfo->maxAnisotropy > 1) {
 354       mag_filter = MAPFILTER_ANISOTROPIC;
 355       min_filter = MAPFILTER_ANISOTROPIC;
 356       max_anisotropy = (pCreateInfo->maxAnisotropy - 2) / 2;
 357    } else {
 358       mag_filter = vk_to_gen_tex_filter[pCreateInfo->magFilter];
 359       min_filter = vk_to_gen_tex_filter[pCreateInfo->minFilter];
 360       max_anisotropy = RATIO21;
 361    }
 362
 363    struct GENX(SAMPLER_STATE) sampler_state = {
 364       .SamplerDisable = false,
 365       .TextureBorderColorMode = DX10OGL,
 366       .LODPreClampMode = 0,
 367 #if ANV_GEN == 8
 368       .BaseMipLevel = 0.0,
 369 #endif
 370       .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
 371       .MagModeFilter = mag_filter,
 372       .MinModeFilter = min_filter,
 373       .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
 374       .AnisotropicAlgorithm = EWAApproximation,
 375       .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
 376       .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
 377       .ChromaKeyEnable = 0,
 378       .ChromaKeyIndex = 0,
 379       .ChromaKeyMode = 0,
 380       .ShadowFunction = vk_to_gen_compare_op[pCreateInfo->compareOp],
 381       .CubeSurfaceControlMode = 0,
 382
 383       .IndirectStatePointer =
 384          device->border_colors.offset +
 385          pCreateInfo->borderColor * sizeof(float) * 4,
 386
 387       .LODClampMagnificationMode = MIPNONE,
 388       .MaximumAnisotropy = max_anisotropy,
 389       .RAddressMinFilterRoundingEnable = 0,
 390       .RAddressMagFilterRoundingEnable = 0,
 391       .VAddressMinFilterRoundingEnable = 0,
 392       .VAddressMagFilterRoundingEnable = 0,
 393       .UAddressMinFilterRoundingEnable = 0,
 394       .UAddressMagFilterRoundingEnable = 0,
 395       .TrilinearFilterQuality = 0,
 396       .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 397       .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 398       .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 399       .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 400    };
 401
 402    GENX(SAMPLER_STATE_pack)(NULL, sampler->state, &sampler_state);
 403
 404    *pSampler = anv_sampler_to_handle(sampler);
 405
 406    return VK_SUCCESS;
 407 }