2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
30 # include "gen9_pack.h"
32 # include "gen8_pack.h"
33 #elif (ANV_IS_HASWELL)
34 # include "gen75_pack.h"
36 # include "gen7_pack.h"
40 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
42 struct anv_device
*device
= cmd_buffer
->device
;
43 struct anv_bo
*scratch_bo
= NULL
;
45 cmd_buffer
->state
.scratch_size
=
46 anv_block_pool_size(&device
->scratch_block_pool
);
47 if (cmd_buffer
->state
.scratch_size
> 0)
48 scratch_bo
= &device
->scratch_block_pool
.bo
;
50 /* XXX: Do we need this on more than just BDW? */
52 /* Emit a render target cache flush.
54 * This isn't documented anywhere in the PRM. However, it seems to be
55 * necessary prior to changing the surface state base adress. Without
56 * this, we get GPU hangs when using multi-level command buffers which
57 * clear depth, reset state base address, and then go render stuff.
59 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
60 .RenderTargetCacheFlushEnable
= true);
63 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
),
64 .GeneralStateBaseAddress
= { scratch_bo
, 0 },
65 .GeneralStateMemoryObjectControlState
= GENX(MOCS
),
66 .GeneralStateBaseAddressModifyEnable
= true,
68 .SurfaceStateBaseAddress
= anv_cmd_buffer_surface_base_address(cmd_buffer
),
69 .SurfaceStateMemoryObjectControlState
= GENX(MOCS
),
70 .SurfaceStateBaseAddressModifyEnable
= true,
72 .DynamicStateBaseAddress
= { &device
->dynamic_state_block_pool
.bo
, 0 },
73 .DynamicStateMemoryObjectControlState
= GENX(MOCS
),
74 .DynamicStateBaseAddressModifyEnable
= true,
76 .IndirectObjectBaseAddress
= { NULL
, 0 },
77 .IndirectObjectMemoryObjectControlState
= GENX(MOCS
),
78 .IndirectObjectBaseAddressModifyEnable
= true,
80 .InstructionBaseAddress
= { &device
->instruction_block_pool
.bo
, 0 },
81 .InstructionMemoryObjectControlState
= GENX(MOCS
),
82 .InstructionBaseAddressModifyEnable
= true,
85 /* Broadwell requires that we specify a buffer size for a bunch of
86 * these fields. However, since we will be growing the BO's live, we
87 * just set them all to the maximum.
89 .GeneralStateBufferSize
= 0xfffff,
90 .GeneralStateBufferSizeModifyEnable
= true,
91 .DynamicStateBufferSize
= 0xfffff,
92 .DynamicStateBufferSizeModifyEnable
= true,
93 .IndirectObjectBufferSize
= 0xfffff,
94 .IndirectObjectBufferSizeModifyEnable
= true,
95 .InstructionBufferSize
= 0xfffff,
96 .InstructionBuffersizeModifyEnable
= true,
100 /* After re-setting the surface state base address, we have to do some
101 * cache flusing so that the sampler engine will pick up the new
102 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
103 * Shared Function > 3D Sampler > State > State Caching (page 96):
105 * Coherency with system memory in the state cache, like the texture
106 * cache is handled partially by software. It is expected that the
107 * command stream or shader will issue Cache Flush operation or
108 * Cache_Flush sampler message to ensure that the L1 cache remains
109 * coherent with system memory.
113 * Whenever the value of the Dynamic_State_Base_Addr,
114 * Surface_State_Base_Addr are altered, the L1 state cache must be
115 * invalidated to ensure the new surface or sampler state is fetched
116 * from system memory.
118 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
119 * which, according the PIPE_CONTROL instruction documentation in the
122 * Setting this bit is independent of any other bit in this packet.
123 * This bit controls the invalidation of the L1 and L2 state caches
124 * at the top of the pipe i.e. at the parsing time.
126 * Unfortunately, experimentation seems to indicate that state cache
127 * invalidation through a PIPE_CONTROL does nothing whatsoever in
128 * regards to surface state and binding tables. In stead, it seems that
129 * invalidating the texture cache is what is actually needed.
131 * XXX: As far as we have been able to determine through
132 * experimentation, shows that flush the texture cache appears to be
133 * sufficient. The theory here is that all of the sampling/rendering
134 * units cache the binding table in the texture cache. However, we have
135 * yet to be able to actually confirm this.
137 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
138 .TextureCacheInvalidationEnable
= true);
141 void genX(CmdPipelineBarrier
)(
142 VkCommandBuffer commandBuffer
,
143 VkPipelineStageFlags srcStageMask
,
144 VkPipelineStageFlags destStageMask
,
146 uint32_t memoryBarrierCount
,
147 const VkMemoryBarrier
* pMemoryBarriers
,
148 uint32_t bufferMemoryBarrierCount
,
149 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
150 uint32_t imageMemoryBarrierCount
,
151 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
153 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
156 struct GENX(PIPE_CONTROL
) cmd
= {
157 GENX(PIPE_CONTROL_header
),
158 .PostSyncOperation
= NoWrite
,
161 /* XXX: I think waitEvent is a no-op on our HW. We should verify that. */
163 if (anv_clear_mask(&srcStageMask
, VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
164 /* This is just what PIPE_CONTROL does */
167 if (anv_clear_mask(&srcStageMask
,
168 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
169 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
170 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
171 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
172 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
173 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
174 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
175 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
176 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
177 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
)) {
178 cmd
.StallAtPixelScoreboard
= true;
181 if (anv_clear_mask(&srcStageMask
,
182 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
183 VK_PIPELINE_STAGE_TRANSFER_BIT
)) {
184 cmd
.CommandStreamerStallEnable
= true;
187 if (anv_clear_mask(&srcStageMask
, VK_PIPELINE_STAGE_HOST_BIT
)) {
188 anv_finishme("VK_PIPE_EVENT_CPU_SIGNAL_BIT");
191 /* On our hardware, all stages will wait for execution as needed. */
194 /* We checked all known VkPipeEventFlags. */
195 anv_assert(srcStageMask
== 0);
197 /* XXX: Right now, we're really dumb and just flush whatever categories
198 * the app asks for. One of these days we may make this a bit better
199 * but right now that's all the hardware allows for in most areas.
201 VkAccessFlags src_flags
= 0;
202 VkAccessFlags dst_flags
= 0;
204 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
205 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
206 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
209 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
210 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
211 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
214 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
215 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
216 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
219 /* The src flags represent how things were used previously. This is
220 * what we use for doing flushes.
222 for_each_bit(b
, src_flags
) {
223 switch ((VkAccessFlagBits
)(1 << b
)) {
224 case VK_ACCESS_SHADER_WRITE_BIT
:
225 cmd
.DCFlushEnable
= true;
227 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
228 cmd
.RenderTargetCacheFlushEnable
= true;
230 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
231 cmd
.DepthCacheFlushEnable
= true;
233 case VK_ACCESS_TRANSFER_WRITE_BIT
:
234 cmd
.RenderTargetCacheFlushEnable
= true;
235 cmd
.DepthCacheFlushEnable
= true;
238 /* Doesn't require a flush */
243 /* The dst flags represent how things will be used in the fugure. This
244 * is what we use for doing cache invalidations.
246 for_each_bit(b
, dst_flags
) {
247 switch ((VkAccessFlagBits
)(1 << b
)) {
248 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
249 case VK_ACCESS_INDEX_READ_BIT
:
250 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
251 cmd
.VFCacheInvalidationEnable
= true;
253 case VK_ACCESS_UNIFORM_READ_BIT
:
254 cmd
.ConstantCacheInvalidationEnable
= true;
256 case VK_ACCESS_SHADER_READ_BIT
:
257 cmd
.TextureCacheInvalidationEnable
= true;
259 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
260 cmd
.TextureCacheInvalidationEnable
= true;
262 case VK_ACCESS_TRANSFER_READ_BIT
:
263 cmd
.TextureCacheInvalidationEnable
= true;
265 case VK_ACCESS_MEMORY_READ_BIT
:
266 break; /* XXX: What is this? */
268 /* Doesn't require a flush */
273 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
274 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &cmd
);
278 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
279 struct anv_bo
*bo
, uint32_t offset
)
281 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
282 GENX(3DSTATE_VERTEX_BUFFERS
));
284 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
285 &(struct GENX(VERTEX_BUFFER_STATE
)) {
286 .VertexBufferIndex
= 32, /* Reserved for this */
287 .AddressModifyEnable
= true,
290 .MemoryObjectControlState
= GENX(MOCS
),
291 .BufferStartingAddress
= { bo
, offset
},
294 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
295 .BufferStartingAddress
= { bo
, offset
},
296 .EndAddress
= { bo
, offset
+ 8 },
302 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
303 uint32_t base_vertex
, uint32_t base_instance
)
305 struct anv_state id_state
=
306 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
308 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
309 ((uint32_t *)id_state
.map
)[1] = base_instance
;
311 if (!cmd_buffer
->device
->info
.has_llc
)
312 anv_state_clflush(id_state
);
314 emit_base_vertex_instance_bo(cmd_buffer
,
315 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
319 VkCommandBuffer commandBuffer
,
320 uint32_t vertexCount
,
321 uint32_t instanceCount
,
322 uint32_t firstVertex
,
323 uint32_t firstInstance
)
325 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
326 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
328 genX(cmd_buffer_flush_state
)(cmd_buffer
);
330 if (cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_basevertex
||
331 cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_baseinstance
)
332 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
334 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
335 .VertexAccessType
= SEQUENTIAL
,
336 .PrimitiveTopologyType
= pipeline
->topology
,
337 .VertexCountPerInstance
= vertexCount
,
338 .StartVertexLocation
= firstVertex
,
339 .InstanceCount
= instanceCount
,
340 .StartInstanceLocation
= firstInstance
,
341 .BaseVertexLocation
= 0);
344 void genX(CmdDrawIndexed
)(
345 VkCommandBuffer commandBuffer
,
347 uint32_t instanceCount
,
349 int32_t vertexOffset
,
350 uint32_t firstInstance
)
352 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
353 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
355 genX(cmd_buffer_flush_state
)(cmd_buffer
);
357 if (cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_basevertex
||
358 cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_baseinstance
)
359 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
361 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
362 .VertexAccessType
= RANDOM
,
363 .PrimitiveTopologyType
= pipeline
->topology
,
364 .VertexCountPerInstance
= indexCount
,
365 .StartVertexLocation
= firstIndex
,
366 .InstanceCount
= instanceCount
,
367 .StartInstanceLocation
= firstInstance
,
368 .BaseVertexLocation
= vertexOffset
);
371 /* Auto-Draw / Indirect Registers */
372 #define GEN7_3DPRIM_END_OFFSET 0x2420
373 #define GEN7_3DPRIM_START_VERTEX 0x2430
374 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
375 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
376 #define GEN7_3DPRIM_START_INSTANCE 0x243C
377 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
380 emit_lrm(struct anv_batch
*batch
,
381 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
383 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
384 .RegisterAddress
= reg
,
385 .MemoryAddress
= { bo
, offset
});
389 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
391 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
),
392 .RegisterOffset
= reg
,
396 void genX(CmdDrawIndirect
)(
397 VkCommandBuffer commandBuffer
,
403 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
404 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
405 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
406 struct anv_bo
*bo
= buffer
->bo
;
407 uint32_t bo_offset
= buffer
->offset
+ offset
;
409 genX(cmd_buffer_flush_state
)(cmd_buffer
);
411 if (cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_basevertex
||
412 cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_baseinstance
)
413 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
415 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
416 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
417 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
418 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
419 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
421 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
422 .IndirectParameterEnable
= true,
423 .VertexAccessType
= SEQUENTIAL
,
424 .PrimitiveTopologyType
= pipeline
->topology
);
427 void genX(CmdDrawIndexedIndirect
)(
428 VkCommandBuffer commandBuffer
,
434 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
435 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
436 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
437 struct anv_bo
*bo
= buffer
->bo
;
438 uint32_t bo_offset
= buffer
->offset
+ offset
;
440 genX(cmd_buffer_flush_state
)(cmd_buffer
);
442 /* TODO: We need to stomp base vertex to 0 somehow */
443 if (cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_basevertex
||
444 cmd_buffer
->state
.pipeline
->vs_prog_data
.uses_baseinstance
)
445 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
447 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
448 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
449 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
450 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
451 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
453 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
454 .IndirectParameterEnable
= true,
455 .VertexAccessType
= RANDOM
,
456 .PrimitiveTopologyType
= pipeline
->topology
);
460 void genX(CmdDispatch
)(
461 VkCommandBuffer commandBuffer
,
466 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
467 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
468 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
470 if (prog_data
->uses_num_work_groups
) {
471 struct anv_state state
=
472 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
473 uint32_t *sizes
= state
.map
;
477 if (!cmd_buffer
->device
->info
.has_llc
)
478 anv_state_clflush(state
);
479 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
480 cmd_buffer
->state
.num_workgroups_bo
=
481 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
484 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
486 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
),
487 .SIMDSize
= prog_data
->simd_size
/ 16,
488 .ThreadDepthCounterMaximum
= 0,
489 .ThreadHeightCounterMaximum
= 0,
490 .ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1,
491 .ThreadGroupIDXDimension
= x
,
492 .ThreadGroupIDYDimension
= y
,
493 .ThreadGroupIDZDimension
= z
,
494 .RightExecutionMask
= pipeline
->cs_right_mask
,
495 .BottomExecutionMask
= 0xffffffff);
497 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
));
500 #define GPGPU_DISPATCHDIMX 0x2500
501 #define GPGPU_DISPATCHDIMY 0x2504
502 #define GPGPU_DISPATCHDIMZ 0x2508
504 void genX(CmdDispatchIndirect
)(
505 VkCommandBuffer commandBuffer
,
509 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
510 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
511 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
512 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
513 struct anv_bo
*bo
= buffer
->bo
;
514 uint32_t bo_offset
= buffer
->offset
+ offset
;
516 if (prog_data
->uses_num_work_groups
) {
517 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
518 cmd_buffer
->state
.num_workgroups_bo
= bo
;
521 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
523 emit_lrm(&cmd_buffer
->batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
524 emit_lrm(&cmd_buffer
->batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
525 emit_lrm(&cmd_buffer
->batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
527 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
),
528 .IndirectParameterEnable
= true,
529 .SIMDSize
= prog_data
->simd_size
/ 16,
530 .ThreadDepthCounterMaximum
= 0,
531 .ThreadHeightCounterMaximum
= 0,
532 .ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1,
533 .RightExecutionMask
= pipeline
->cs_right_mask
,
534 .BottomExecutionMask
= 0xffffffff);
536 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
));
540 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
542 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
543 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
),
547 .PipelineSelection
= _3D
);
548 cmd_buffer
->state
.current_pipeline
= _3D
;
553 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
555 struct anv_device
*device
= cmd_buffer
->device
;
556 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
557 const struct anv_image_view
*iview
=
558 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
559 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
560 const struct anv_format
*anv_format
=
561 iview
? anv_format_for_vk_format(iview
->vk_format
) : NULL
;
562 const bool has_depth
= iview
&& anv_format
->has_depth
;
563 const bool has_stencil
= iview
&& anv_format
->has_stencil
;
565 /* FIXME: Implement the PMA stall W/A */
566 /* FIXME: Width and Height are wrong */
568 /* Emit 3DSTATE_DEPTH_BUFFER */
570 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
),
571 .SurfaceType
= SURFTYPE_2D
,
572 .DepthWriteEnable
= true,
573 .StencilWriteEnable
= has_stencil
,
574 .HierarchicalDepthBufferEnable
= false,
575 .SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
576 &image
->depth_surface
.isl
),
577 .SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1,
578 .SurfaceBaseAddress
= {
580 .offset
= image
->depth_surface
.offset
,
582 .Height
= fb
->height
- 1,
583 .Width
= fb
->width
- 1,
586 .MinimumArrayElement
= 0,
587 .DepthBufferObjectControlState
= GENX(MOCS
),
589 .SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2,
591 .RenderTargetViewExtent
= 1 - 1);
593 /* Even when no depth buffer is present, the hardware requires that
594 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
596 * If a null depth buffer is bound, the driver must instead bind depth as:
597 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
598 * 3DSTATE_DEPTH.Width = 1
599 * 3DSTATE_DEPTH.Height = 1
600 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
601 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
602 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
603 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
604 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
606 * The PRM is wrong, though. The width and height must be programmed to
607 * actual framebuffer's width and height, even when neither depth buffer
608 * nor stencil buffer is present.
610 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
),
611 .SurfaceType
= SURFTYPE_2D
,
612 .SurfaceFormat
= D16_UNORM
,
613 .Width
= fb
->width
- 1,
614 .Height
= fb
->height
- 1,
615 .StencilWriteEnable
= has_stencil
);
618 /* Emit 3DSTATE_STENCIL_BUFFER */
620 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
),
621 #if ANV_GEN >= 8 || ANV_IS_HASWELL
622 .StencilBufferEnable
= true,
624 .StencilBufferObjectControlState
= GENX(MOCS
),
626 /* Stencil buffers have strange pitch. The PRM says:
628 * The pitch must be set to 2x the value computed based on width,
629 * as the stencil buffer is stored with two rows interleaved.
631 .SurfacePitch
= 2 * image
->stencil_surface
.isl
.row_pitch
- 1,
634 .SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2,
636 .SurfaceBaseAddress
= {
638 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
641 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
));
644 /* Disable hierarchial depth buffers. */
645 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
));
647 /* Clear the clear params. */
648 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
));
652 * @see anv_cmd_buffer_set_subpass()
655 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
656 struct anv_subpass
*subpass
)
658 cmd_buffer
->state
.subpass
= subpass
;
660 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
662 cmd_buffer_emit_depth_stencil(cmd_buffer
);
665 void genX(CmdBeginRenderPass
)(
666 VkCommandBuffer commandBuffer
,
667 const VkRenderPassBeginInfo
* pRenderPassBegin
,
668 VkSubpassContents contents
)
670 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
671 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
672 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
674 cmd_buffer
->state
.framebuffer
= framebuffer
;
675 cmd_buffer
->state
.pass
= pass
;
676 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
678 genX(flush_pipeline_select_3d
)(cmd_buffer
);
680 const VkRect2D
*render_area
= &pRenderPassBegin
->renderArea
;
682 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DRAWING_RECTANGLE
),
683 .ClippedDrawingRectangleYMin
= render_area
->offset
.y
,
684 .ClippedDrawingRectangleXMin
= render_area
->offset
.x
,
685 .ClippedDrawingRectangleYMax
=
686 render_area
->offset
.y
+ render_area
->extent
.height
- 1,
687 .ClippedDrawingRectangleXMax
=
688 render_area
->offset
.x
+ render_area
->extent
.width
- 1,
689 .DrawingRectangleOriginY
= 0,
690 .DrawingRectangleOriginX
= 0);
692 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
693 anv_cmd_buffer_clear_subpass(cmd_buffer
);
696 void genX(CmdNextSubpass
)(
697 VkCommandBuffer commandBuffer
,
698 VkSubpassContents contents
)
700 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
702 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
704 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
705 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
706 anv_cmd_buffer_clear_subpass(cmd_buffer
);
709 void genX(CmdEndRenderPass
)(
710 VkCommandBuffer commandBuffer
)
712 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
714 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
716 /* Emit a flushing pipe control at the end of a pass. This is kind of a
717 * hack but it ensures that render targets always actually get written.
718 * Eventually, we should do flushing based on image format transitions
719 * or something of that nature.
721 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
722 .PostSyncOperation
= NoWrite
,
723 .RenderTargetCacheFlushEnable
= true,
724 .InstructionCacheInvalidateEnable
= true,
725 .DepthCacheFlushEnable
= true,
726 .VFCacheInvalidationEnable
= true,
727 .TextureCacheInvalidationEnable
= true,
728 .CommandStreamerStallEnable
= true);