2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
29 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
30 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
31 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
32 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
33 default: unreachable("Invalid component");
37 return VFCOMP_STORE_SRC
;
38 } else if (comp
< 3) {
39 return VFCOMP_STORE_0
;
40 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
41 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
43 return VFCOMP_STORE_1_INT
;
46 return VFCOMP_STORE_1_FP
;
51 emit_vertex_input(struct anv_pipeline
*pipeline
,
52 const VkPipelineVertexInputStateCreateInfo
*info
,
53 const struct anv_graphics_pipeline_create_info
*extra
)
56 if (extra
&& extra
->disable_vs
) {
57 /* If the VS is disabled, just assume the user knows what they're
58 * doing and apply the layout blindly. This can only come from
59 * meta, so this *should* be safe.
62 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++)
63 elements
|= (1 << info
->pVertexAttributeDescriptions
[i
].location
);
65 /* Pull inputs_read out of the VS prog data */
66 uint64_t inputs_read
= pipeline
->vs_prog_data
.inputs_read
;
67 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
68 elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
72 /* On BDW+, we only need to allocate space for base ids. Setting up
73 * the actual vertex and instance id is a separate packet.
75 const bool needs_svgs_elem
= pipeline
->vs_prog_data
.uses_basevertex
||
76 pipeline
->vs_prog_data
.uses_baseinstance
;
78 /* On Haswell and prior, vertex and instance id are created by using the
79 * ComponentControl fields, so we need an element for any of them.
81 const bool needs_svgs_elem
= pipeline
->vs_prog_data
.uses_vertexid
||
82 pipeline
->vs_prog_data
.uses_instanceid
||
83 pipeline
->vs_prog_data
.uses_basevertex
||
84 pipeline
->vs_prog_data
.uses_baseinstance
;
87 uint32_t elem_count
= __builtin_popcount(elements
) + needs_svgs_elem
;
91 const uint32_t num_dwords
= 1 + elem_count
* 2;
92 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
93 GENX(3DSTATE_VERTEX_ELEMENTS
));
94 memset(p
+ 1, 0, (num_dwords
- 1) * 4);
97 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
98 const VkVertexInputAttributeDescription
*desc
=
99 &info
->pVertexAttributeDescriptions
[i
];
100 enum isl_format format
= anv_get_isl_format(desc
->format
,
101 VK_IMAGE_ASPECT_COLOR_BIT
,
102 VK_IMAGE_TILING_LINEAR
,
105 assert(desc
->binding
< 32);
107 if ((elements
& (1 << desc
->location
)) == 0)
108 continue; /* Binding unused */
110 uint32_t slot
= __builtin_popcount(elements
& ((1 << desc
->location
) - 1));
112 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
113 .VertexBufferIndex
= desc
->binding
,
115 .SourceElementFormat
= format
,
116 .EdgeFlagEnable
= false,
117 .SourceElementOffset
= desc
->offset
,
118 .Component0Control
= vertex_element_comp_control(format
, 0),
119 .Component1Control
= vertex_element_comp_control(format
, 1),
120 .Component2Control
= vertex_element_comp_control(format
, 2),
121 .Component3Control
= vertex_element_comp_control(format
, 3),
123 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
126 /* On Broadwell and later, we have a separate VF_INSTANCING packet
127 * that controls instancing. On Haswell and prior, that's part of
128 * VERTEX_BUFFER_STATE which we emit later.
130 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
),
131 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
132 .VertexElementIndex
= slot
,
133 /* Vulkan so far doesn't have an instance divisor, so
134 * this is always 1 (ignored if not instancing). */
135 .InstanceDataStepRate
= 1);
139 const uint32_t id_slot
= __builtin_popcount(elements
);
140 if (needs_svgs_elem
) {
141 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
142 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
143 * Control field is set to something other than VFCOMP_STORE_SRC,
144 * no higher-numbered Component Control fields may be set to
147 * This means, that if we have BaseInstance, we need BaseVertex as
148 * well. Just do all or nothing.
150 uint32_t base_ctrl
= (pipeline
->vs_prog_data
.uses_basevertex
||
151 pipeline
->vs_prog_data
.uses_baseinstance
) ?
152 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
154 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
155 .VertexBufferIndex
= 32, /* Reserved for this */
157 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
158 .Component0Control
= base_ctrl
,
159 .Component1Control
= base_ctrl
,
161 .Component2Control
= VFCOMP_STORE_0
,
162 .Component3Control
= VFCOMP_STORE_0
,
164 .Component2Control
= VFCOMP_STORE_VID
,
165 .Component3Control
= VFCOMP_STORE_IID
,
168 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
172 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
),
173 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
174 .VertexIDComponentNumber
= 2,
175 .VertexIDElementOffset
= id_slot
,
176 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
177 .InstanceIDComponentNumber
= 3,
178 .InstanceIDElementOffset
= id_slot
);
183 emit_urb_setup(struct anv_pipeline
*pipeline
)
186 struct anv_device
*device
= pipeline
->device
;
188 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
190 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
191 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
192 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
193 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
194 * needs to be sent before any combination of VS associated 3DSTATE."
196 anv_batch_emit(&pipeline
->batch
, GEN7_PIPE_CONTROL
,
197 .DepthStallEnable
= true,
198 .PostSyncOperation
= WriteImmediateData
,
199 .Address
= { &device
->workaround_bo
, 0 });
202 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
),
203 .ConstantBufferOffset
= 0,
204 .ConstantBufferSize
= 4);
205 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS
),
206 .ConstantBufferOffset
= 4,
207 .ConstantBufferSize
= 4);
208 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
),
209 .ConstantBufferOffset
= 8,
210 .ConstantBufferSize
= 4);
212 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_URB_VS
),
213 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
214 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
215 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
217 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_URB_GS
),
218 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
219 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
220 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
222 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_URB_HS
),
223 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
224 .HSURBEntryAllocationSize
= 0,
225 .HSNumberofURBEntries
= 0);
227 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_URB_DS
),
228 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
229 .DSURBEntryAllocationSize
= 0,
230 .DSNumberofURBEntries
= 0);
233 static inline uint32_t
234 scratch_space(const struct brw_stage_prog_data
*prog_data
)
236 return ffs(prog_data
->total_scratch
/ 2048);
239 static const uint32_t vk_to_gen_cullmode
[] = {
240 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
241 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
242 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
243 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
246 static const uint32_t vk_to_gen_fillmode
[] = {
247 [VK_POLYGON_MODE_FILL
] = RASTER_SOLID
,
248 [VK_POLYGON_MODE_LINE
] = RASTER_WIREFRAME
,
249 [VK_POLYGON_MODE_POINT
] = RASTER_POINT
,
252 static const uint32_t vk_to_gen_front_face
[] = {
253 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
254 [VK_FRONT_FACE_CLOCKWISE
] = 0
257 static const uint32_t vk_to_gen_logic_op
[] = {
258 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
259 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
260 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
261 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
262 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
263 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
264 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
265 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
266 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
267 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
268 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
269 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
270 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
271 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
272 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
273 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
276 static const uint32_t vk_to_gen_blend
[] = {
277 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
278 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
279 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
280 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
281 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
282 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
283 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
284 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
285 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
286 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
287 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
288 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
289 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
290 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
291 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
292 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
293 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
294 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
295 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
298 static const uint32_t vk_to_gen_blend_op
[] = {
299 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
300 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
301 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
302 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
303 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
306 static const uint32_t vk_to_gen_compare_op
[] = {
307 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
308 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
309 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
310 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
311 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
312 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
313 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
314 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
317 static const uint32_t vk_to_gen_stencil_op
[] = {
318 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
319 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
320 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
321 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
322 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
323 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
324 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
325 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,