2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 void PRINTFLIKE(3, 4) UNUSED
35 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
41 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
44 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
48 isl_device_init(struct isl_device
*dev
,
49 const struct brw_device_info
*info
)
52 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
54 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
55 * device properties at buildtime. Verify that the macros with the device
56 * properties chosen during runtime.
58 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
59 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
61 /* Did we break hiz or stencil? */
62 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
63 assert(info
->has_hiz_and_separate_stencil
);
64 if (info
->must_use_separate_stencil
)
65 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
69 isl_format_has_sint_channel(enum isl_format fmt
)
71 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
73 return fmtl
->channels
.r
.type
== ISL_SINT
||
74 fmtl
->channels
.g
.type
== ISL_SINT
||
75 fmtl
->channels
.b
.type
== ISL_SINT
||
76 fmtl
->channels
.a
.type
== ISL_SINT
||
77 fmtl
->channels
.l
.type
== ISL_SINT
||
78 fmtl
->channels
.i
.type
== ISL_SINT
||
79 fmtl
->channels
.p
.type
== ISL_SINT
||
80 fmtl
->channels
.g
.type
== ISL_SINT
;
84 * @param[out] info is written only on success
87 isl_tiling_get_info(const struct isl_device
*dev
,
88 enum isl_tiling tiling
,
89 uint32_t format_block_size
,
90 struct isl_tile_info
*tile_info
)
92 const uint32_t bs
= format_block_size
;
93 uint32_t width
, height
;
98 case ISL_TILING_LINEAR
:
114 /* XXX: Should W tile be same as Y? */
120 case ISL_TILING_Ys
: {
121 if (ISL_DEV_GEN(dev
) < 9)
124 if (!isl_is_pow2(bs
))
127 bool is_Ys
= tiling
== ISL_TILING_Ys
;
129 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
130 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
135 *tile_info
= (struct isl_tile_info
) {
139 .size
= width
* height
,
146 isl_tiling_get_extent(const struct isl_device
*dev
,
147 enum isl_tiling tiling
,
148 uint32_t format_block_size
,
149 struct isl_extent2d
*e
)
151 struct isl_tile_info tile_info
;
152 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
153 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
157 * @param[out] tiling is set only on success
160 isl_surf_choose_tiling(const struct isl_device
*dev
,
161 const struct isl_surf_init_info
*restrict info
,
162 enum isl_tiling
*tiling
)
164 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
166 if (ISL_DEV_GEN(dev
) >= 7) {
167 gen7_filter_tiling(dev
, info
, &tiling_flags
);
169 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
170 gen7_filter_tiling(dev
, info
, &tiling_flags
);
173 #define CHOOSE(__tiling) \
175 if (tiling_flags & (1u << (__tiling))) { \
176 *tiling = (__tiling); \
181 /* Of the tiling modes remaining, choose the one that offers the best
184 CHOOSE(ISL_TILING_Ys
);
185 CHOOSE(ISL_TILING_Yf
);
186 CHOOSE(ISL_TILING_Y0
);
187 CHOOSE(ISL_TILING_X
);
188 CHOOSE(ISL_TILING_W
);
189 CHOOSE(ISL_TILING_LINEAR
);
193 /* No tiling mode accomodates the inputs. */
198 isl_choose_msaa_layout(const struct isl_device
*dev
,
199 const struct isl_surf_init_info
*info
,
200 enum isl_tiling tiling
,
201 enum isl_msaa_layout
*msaa_layout
)
203 if (ISL_DEV_GEN(dev
) >= 8) {
204 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
205 } else if (ISL_DEV_GEN(dev
) >= 7) {
206 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
207 } else if (ISL_DEV_GEN(dev
) >= 6) {
208 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
210 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
215 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
216 uint32_t *width
, uint32_t *height
)
218 assert(isl_is_pow2(samples
));
220 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
223 * If the surface is multisampled and it is a depth or stencil surface
224 * or Multisampled Surface StorageFormat in SURFACE_STATE is
225 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
228 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
229 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
232 static enum isl_array_pitch_span
233 isl_choose_array_pitch_span(const struct isl_device
*dev
,
234 const struct isl_surf_init_info
*restrict info
,
235 enum isl_dim_layout dim_layout
,
236 const struct isl_extent4d
*phys_level0_sa
)
238 switch (dim_layout
) {
239 case ISL_DIM_LAYOUT_GEN9_1D
:
240 if (ISL_DEV_GEN(dev
) >= 9)
241 isl_finishme("%s:%s: [SKL+] 1d surface layout", __FILE__
, __func__
);
244 case ISL_DIM_LAYOUT_GEN4_2D
:
245 if (ISL_DEV_GEN(dev
) >= 8) {
246 /* QPitch becomes programmable in Broadwell. So choose the
247 * most compact QPitch possible in order to conserve memory.
249 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
250 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
252 * - Software must ensure that this field is set to a value
253 * sufficiently large such that the array slices in the surface
254 * do not overlap. Refer to the Memory Data Formats section for
255 * information on how surfaces are stored in memory.
257 * - This field specifies the distance in rows between array
258 * slices. It is used only in the following cases:
260 * - Surface Array is enabled OR
261 * - Number of Mulitsamples is not NUMSAMPLES_1 and
262 * Multisampled Surface Storage Format set to MSFMT_MSS OR
263 * - Surface Type is SURFTYPE_CUBE
265 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
266 } else if (ISL_DEV_GEN(dev
) >= 7) {
267 /* Note that Ivybridge introduces
268 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
269 * driver more control over the QPitch.
272 if (phys_level0_sa
->array_len
== 1) {
273 /* The hardware will never use the QPitch. So choose the most
274 * compact QPitch possible in order to conserve memory.
276 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
279 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
280 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
281 * Section 6.18.4.7: Surface Arrays (p112):
283 * If Surface Array Spacing is set to ARYSPC_FULL (note that
284 * the depth buffer and stencil buffer have an implied value of
287 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
290 if (info
->levels
== 1) {
291 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
294 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
297 return ISL_ARRAY_PITCH_SPAN_FULL
;
298 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
299 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
300 isl_surf_usage_is_stencil(info
->usage
)) {
301 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
302 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
304 * The separate stencil buffer does not support mip mapping, thus
305 * the storage for LODs other than LOD 0 is not needed.
307 assert(info
->levels
== 1);
308 assert(phys_level0_sa
->array_len
== 1);
309 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
311 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
312 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
313 isl_surf_usage_is_stencil(info
->usage
)) {
314 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
315 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
317 * The separate stencil buffer does not support mip mapping,
318 * thus the storage for LODs other than LOD 0 is not needed.
320 assert(info
->levels
== 1);
321 assert(phys_level0_sa
->array_len
== 1);
322 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
325 if (phys_level0_sa
->array_len
== 1) {
326 /* The hardware will never use the QPitch. So choose the most
327 * compact QPitch possible in order to conserve memory.
329 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
332 return ISL_ARRAY_PITCH_SPAN_FULL
;
335 case ISL_DIM_LAYOUT_GEN4_3D
:
336 /* The hardware will never use the QPitch. So choose the most
337 * compact QPitch possible in order to conserve memory.
339 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
342 unreachable("bad isl_dim_layout");
343 return ISL_ARRAY_PITCH_SPAN_FULL
;
347 isl_choose_lod_alignment_el(const struct isl_device
*dev
,
348 const struct isl_surf_init_info
*restrict info
,
349 enum isl_tiling tiling
,
350 enum isl_msaa_layout msaa_layout
,
351 struct isl_extent3d
*lod_align_el
)
353 if (ISL_DEV_GEN(dev
) >= 9) {
354 gen9_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
,
356 } else if (ISL_DEV_GEN(dev
) >= 8) {
357 gen8_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
,
359 } else if (ISL_DEV_GEN(dev
) >= 7) {
360 gen7_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
,
362 } else if (ISL_DEV_GEN(dev
) >= 6) {
363 gen6_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
,
366 gen4_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
,
371 static enum isl_dim_layout
372 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
373 enum isl_surf_dim logical_dim
)
375 if (ISL_DEV_GEN(dev
) >= 9) {
376 switch (logical_dim
) {
377 case ISL_SURF_DIM_1D
:
378 return ISL_DIM_LAYOUT_GEN9_1D
;
379 case ISL_SURF_DIM_2D
:
380 case ISL_SURF_DIM_3D
:
381 return ISL_DIM_LAYOUT_GEN4_2D
;
384 switch (logical_dim
) {
385 case ISL_SURF_DIM_1D
:
386 case ISL_SURF_DIM_2D
:
387 return ISL_DIM_LAYOUT_GEN4_2D
;
388 case ISL_SURF_DIM_3D
:
389 return ISL_DIM_LAYOUT_GEN4_3D
;
393 unreachable("bad isl_surf_dim");
394 return ISL_DIM_LAYOUT_GEN4_2D
;
398 * Calculate the physical extent of the surface's first level, in units of
402 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
403 const struct isl_surf_init_info
*restrict info
,
404 enum isl_dim_layout dim_layout
,
405 enum isl_tiling tiling
,
406 enum isl_msaa_layout msaa_layout
,
407 struct isl_extent4d
*phys_level0_sa
)
409 if (isl_format_is_yuv(info
->format
))
410 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
413 case ISL_SURF_DIM_1D
:
414 assert(info
->height
== 1);
415 assert(info
->depth
== 1);
416 assert(info
->samples
== 1);
418 switch (dim_layout
) {
419 case ISL_DIM_LAYOUT_GEN4_3D
:
420 unreachable("bad isl_dim_layout");
422 case ISL_DIM_LAYOUT_GEN9_1D
:
423 if (ISL_DEV_GEN(dev
) >= 9)
424 isl_finishme("%s:%s: [SKL+] 1d surface layout", __FILE__
, __func__
);
427 case ISL_DIM_LAYOUT_GEN4_2D
:
428 *phys_level0_sa
= (struct isl_extent4d
) {
432 .a
= info
->array_len
,
438 case ISL_SURF_DIM_2D
:
439 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
441 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
442 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
444 switch (msaa_layout
) {
445 case ISL_MSAA_LAYOUT_NONE
:
446 assert(info
->depth
== 1);
447 assert(info
->samples
== 1);
449 *phys_level0_sa
= (struct isl_extent4d
) {
453 .a
= info
->array_len
,
457 case ISL_MSAA_LAYOUT_ARRAY
:
458 assert(info
->depth
== 1);
459 assert(info
->array_len
== 1);
460 assert(!isl_format_is_compressed(info
->format
));
462 *phys_level0_sa
= (struct isl_extent4d
) {
470 case ISL_MSAA_LAYOUT_INTERLEAVED
:
471 assert(info
->depth
== 1);
472 assert(info
->array_len
== 1);
473 assert(!isl_format_is_compressed(info
->format
));
475 *phys_level0_sa
= (struct isl_extent4d
) {
482 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
489 case ISL_SURF_DIM_3D
:
490 assert(info
->array_len
== 1);
491 assert(info
->samples
== 1);
493 switch (dim_layout
) {
494 case ISL_DIM_LAYOUT_GEN9_1D
:
495 unreachable("bad isl_dim_layout");
497 case ISL_DIM_LAYOUT_GEN4_2D
:
498 assert(ISL_DEV_GEN(dev
) >= 9);
500 *phys_level0_sa
= (struct isl_extent4d
) {
508 case ISL_DIM_LAYOUT_GEN4_3D
:
509 assert(ISL_DEV_GEN(dev
) < 9);
510 *phys_level0_sa
= (struct isl_extent4d
) {
523 * A variant of isl_calc_phys_slice0_extent_sa() specific to
524 * ISL_DIM_LAYOUT_GEN4_2D.
527 isl_calc_phys_slice0_extent_sa_gen4_2d(
528 const struct isl_device
*dev
,
529 const struct isl_surf_init_info
*restrict info
,
530 enum isl_msaa_layout msaa_layout
,
531 const struct isl_extent3d
*lod_align_sa
,
532 const struct isl_extent4d
*phys_level0_sa
,
533 struct isl_extent2d
*phys_slice0_sa
)
535 assert(phys_level0_sa
->depth
== 1);
537 uint32_t slice_top_w
= 0;
538 uint32_t slice_bottom_w
= 0;
539 uint32_t slice_left_h
= 0;
540 uint32_t slice_right_h
= 0;
542 uint32_t W0
= phys_level0_sa
->w
;
543 uint32_t H0
= phys_level0_sa
->h
;
545 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
546 uint32_t W
= isl_minify(W0
, l
);
547 uint32_t H
= isl_minify(H0
, l
);
549 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
550 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
553 * If the surface is multisampled and it is a depth or stencil
554 * surface or Multisampled Surface StorageFormat in
555 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
556 * adjusted as follows before proceeding: [...]
558 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
561 uint32_t w
= isl_align_npot(W
, lod_align_sa
->w
);
562 uint32_t h
= isl_align_npot(H
, lod_align_sa
->h
);
578 *phys_slice0_sa
= (struct isl_extent2d
) {
579 .w
= MAX(slice_top_w
, slice_bottom_w
),
580 .h
= MAX(slice_left_h
, slice_right_h
),
585 * A variant of isl_calc_phys_slice0_extent_sa() specific to
586 * ISL_DIM_LAYOUT_GEN4_3D.
589 isl_calc_phys_slice0_extent_sa_gen4_3d(
590 const struct isl_device
*dev
,
591 const struct isl_surf_init_info
*restrict info
,
592 const struct isl_extent3d
*lod_align_sa
,
593 const struct isl_extent4d
*phys_level0_sa
,
594 struct isl_extent2d
*phys_slice0_sa
)
596 assert(info
->samples
== 1);
597 assert(phys_level0_sa
->array_len
== 1);
599 uint32_t slice_w
= 0;
600 uint32_t slice_h
= 0;
602 uint32_t W0
= phys_level0_sa
->w
;
603 uint32_t H0
= phys_level0_sa
->h
;
604 uint32_t D0
= phys_level0_sa
->d
;
606 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
607 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), lod_align_sa
->w
);
608 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), lod_align_sa
->h
);
609 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), lod_align_sa
->d
);
611 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
612 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
614 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
615 slice_h
+= level_h
* max_layers_vert
;
618 *phys_slice0_sa
= (struct isl_extent2d
) {
625 * Calculate the physical extent of the surface's first array slice, in units
626 * of surface samples. The result is aligned to \a lod_align_sa.
629 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
630 const struct isl_surf_init_info
*restrict info
,
631 enum isl_dim_layout dim_layout
,
632 enum isl_msaa_layout msaa_layout
,
633 const struct isl_extent3d
*lod_align_sa
,
634 const struct isl_extent4d
*phys_level0_sa
,
635 struct isl_extent2d
*phys_slice0_sa
)
637 switch (dim_layout
) {
638 case ISL_DIM_LAYOUT_GEN9_1D
:
639 if (ISL_DEV_GEN(dev
) >= 9)
640 isl_finishme("%s:%s: [SKL+] physical layout of 1d surfaces",
643 case ISL_DIM_LAYOUT_GEN4_2D
:
644 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
645 lod_align_sa
, phys_level0_sa
,
648 case ISL_DIM_LAYOUT_GEN4_3D
:
649 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, lod_align_sa
,
650 phys_level0_sa
, phys_slice0_sa
);
656 * Calculate the pitch between physical array slices, in units of rows of
657 * surface samples. The result is aligned to \a lod_align_sa.
660 isl_calc_array_pitch_sa_rows(const struct isl_device
*dev
,
661 const struct isl_surf_init_info
*restrict info
,
662 enum isl_dim_layout dim_layout
,
663 enum isl_array_pitch_span array_pitch_span
,
664 const struct isl_extent3d
*lod_align_sa
,
665 const struct isl_extent4d
*phys_level0_sa
,
666 const struct isl_extent2d
*phys_slice0_sa
)
668 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
670 switch (dim_layout
) {
671 case ISL_DIM_LAYOUT_GEN9_1D
:
672 if (ISL_DEV_GEN(dev
) >= 9)
673 isl_finishme("%s:%s: [SKL+] physical layout of 1d surfaces",
677 case ISL_DIM_LAYOUT_GEN4_2D
:
678 switch (array_pitch_span
) {
679 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
680 return isl_align_npot(phys_slice0_sa
->h
, lod_align_sa
->h
);
681 case ISL_ARRAY_PITCH_SPAN_FULL
: {
682 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
683 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
684 * Surfaces >> Surface Arrays.
686 uint32_t H0_sa
= phys_level0_sa
->h
;
687 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
689 uint32_t h0_sa
= isl_align_npot(H0_sa
, lod_align_sa
->h
);
690 uint32_t h1_sa
= isl_align_npot(H1_sa
, lod_align_sa
->h
);
693 if (ISL_DEV_GEN(dev
) >= 7) {
694 /* The QPitch equation changed slightly in Ivybridge. */
700 uint32_t pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* lod_align_sa
->h
);
702 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
703 (info
->height
% 4 == 1)) {
704 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
705 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
707 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
708 * the value calculated in the equation above , for every
709 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
711 * XXX(chadv): Is the errata natural corollary of the physical
712 * layout of interleaved samples?
717 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
719 return pitch_sa_rows
;
725 case ISL_DIM_LAYOUT_GEN4_3D
:
726 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
727 return isl_align_npot(phys_slice0_sa
->h
, lod_align_sa
->h
);
730 unreachable("bad isl_dim_layout");
735 * Calculate the pitch of each surface row, in bytes.
738 isl_calc_row_pitch(const struct isl_device
*dev
,
739 const struct isl_surf_init_info
*restrict info
,
740 const struct isl_tile_info
*tile_info
,
741 const struct isl_extent3d
*lod_align_sa
,
742 const struct isl_extent2d
*phys_slice0_sa
)
744 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
746 uint32_t row_pitch
= info
->min_pitch
;
748 /* First, align the surface to a cache line boundary, as the PRM explains
751 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
752 * Formats >> Surface Padding Requirements >> Render Target and Media
755 * The data port accesses data (pixels) outside of the surface if they
756 * are contained in the same cache request as pixels that are within the
757 * surface. These pixels will not be returned by the requesting message,
758 * however if these pixels lie outside of defined pages in the GTT,
759 * a GTT error will result when the cache request is processed. In order
760 * to avoid these GTT errors, “padding” at the bottom of the surface is
761 * sometimes necessary.
763 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
764 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
766 * The sampling engine accesses texels outside of the surface if they
767 * are contained in the same cache line as texels that are within the
768 * surface. These texels will not participate in any calculation
769 * performed by the sampling engine and will not affect the result of
770 * any sampling engine operation, however if these texels lie outside of
771 * defined pages in the GTT, a GTT error will result when the cache line
772 * is accessed. In order to avoid these GTT errors, “padding” at the
773 * bottom and right side of a sampling engine surface is sometimes
776 * It is possible that a cache line will straddle a page boundary if the
777 * base address or pitch is not aligned. All pages included in the cache
778 * lines that are part of the surface must map to valid GTT entries to
779 * avoid errors. To determine the necessary padding on the bottom and
780 * right side of the surface, refer to the table in Alignment Unit Size
781 * section for the i and j parameters for the surface format in use. The
782 * surface must then be extended to the next multiple of the alignment
783 * unit size in each dimension, and all texels contained in this
784 * extended surface must have valid GTT entries.
786 * For example, suppose the surface size is 15 texels by 10 texels and
787 * the alignment parameters are i=4 and j=2. In this case, the extended
788 * surface would be 16 by 10. Note that these calculations are done in
789 * texels, and must be converted to bytes based on the surface format
790 * being used to determine whether additional pages need to be defined.
792 row_pitch
= MAX(row_pitch
,
793 fmtl
->bs
* isl_align_div_npot(phys_slice0_sa
->w
, fmtl
->bw
));
795 switch (tile_info
->tiling
) {
796 case ISL_TILING_LINEAR
:
797 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
798 * RENDER_SURFACE_STATE Surface Pitch (p349):
800 * - For linear render target surfaces and surfaces accessed with the
801 * typed data port messages, the pitch must be a multiple of the
802 * element size for non-YUV surface formats. Pitch must be
803 * a multiple of 2 * element size for YUV surface formats.
805 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
806 * ignore because isl doesn't do buffers.]
808 * - For other linear surfaces, the pitch can be any multiple of
811 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
812 if (isl_format_is_yuv(info
->format
)) {
813 row_pitch
= isl_align(row_pitch
, fmtl
->bs
);
815 row_pitch
= isl_align(row_pitch
, 2 * fmtl
->bs
);
820 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
821 * RENDER_SURFACE_STATE Surface Pitch (p349):
823 * - For tiled surfaces, the pitch must be a multiple of the tile
826 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
834 * Calculate the surface's total height, including padding, in units of
838 isl_calc_total_height_el(const struct isl_device
*dev
,
839 const struct isl_surf_init_info
*restrict info
,
840 const struct isl_tile_info
*tile_info
,
841 uint32_t phys_array_len
,
843 uint32_t array_pitch_el_rows
)
845 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
847 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
848 uint32_t pad_bytes
= 0;
850 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
851 * Formats >> Surface Padding Requirements >> Render Target and Media
854 * The data port accesses data (pixels) outside of the surface if they
855 * are contained in the same cache request as pixels that are within the
856 * surface. These pixels will not be returned by the requesting message,
857 * however if these pixels lie outside of defined pages in the GTT,
858 * a GTT error will result when the cache request is processed. In
859 * order to avoid these GTT errors, “padding” at the bottom of the
860 * surface is sometimes necessary.
862 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
863 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
865 * ... Lots of padding requirements, all listed separately below.
868 /* We can safely ignore the first padding requirement, quoted below,
869 * because isl doesn't do buffers.
871 * - [pre-BDW] For buffers, which have no inherent “height,” padding
872 * requirements are different. A buffer must be padded to the next
873 * multiple of 256 array elements, with an additional 16 bytes added
874 * beyond that to account for the L1 cache line.
878 * - For compressed textures [...], padding at the bottom of the surface
879 * is to an even compressed row.
881 if (isl_format_is_compressed(info
->format
))
882 total_h_el
= isl_align(total_h_el
, 2);
885 * - For cube surfaces, an additional two rows of padding are required
886 * at the bottom of the surface.
888 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
892 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
893 * additional padding is required. These surfaces require an extra row
894 * plus 16 bytes of padding at the bottom in addition to the general
895 * padding requirements.
897 if (isl_format_is_yuv(info
->format
) &&
898 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
904 * - For linear surfaces, additional padding of 64 bytes is required at
905 * the bottom of the surface. This is in addition to the padding
908 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
911 /* The below text weakens, not strengthens, the padding requirements for
912 * linear surfaces. Therefore we can safely ignore it.
914 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
915 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
916 * padding requirement is to the next aligned 64-byte boundary beyond
917 * the end of the surface. The rest of the padding requirements
918 * documented above do not apply to these surfaces.
922 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
923 * height % 4 != 0, the surface must be padded with
924 * 4-(height % 4)*Surface Pitch # of bytes.
926 if (ISL_DEV_GEN(dev
) >= 9 &&
927 tile_info
->tiling
== ISL_TILING_LINEAR
&&
928 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
929 total_h_el
= isl_align(total_h_el
, 4);
933 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
934 * to 4 times the Surface Pitch # of bytes
936 if (ISL_DEV_GEN(dev
) >= 9 &&
937 tile_info
->tiling
== ISL_TILING_LINEAR
&&
938 info
->dim
== ISL_SURF_DIM_1D
) {
942 /* Be sloppy. Align any leftover padding to a row boundary. */
943 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
949 isl_surf_init_s(const struct isl_device
*dev
,
950 struct isl_surf
*surf
,
951 const struct isl_surf_init_info
*restrict info
)
953 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
955 const struct isl_extent4d logical_level0_px
= {
959 .a
= info
->array_len
,
962 enum isl_dim_layout dim_layout
=
963 isl_surf_choose_dim_layout(dev
, info
->dim
);
965 enum isl_tiling tiling
;
966 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
969 struct isl_tile_info tile_info
;
970 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
973 enum isl_msaa_layout msaa_layout
;
974 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
977 struct isl_extent3d lod_align_el
;
978 isl_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
, &lod_align_el
);
980 struct isl_extent3d lod_align_sa
=
981 isl_extent3d_el_to_sa(info
->format
, lod_align_el
);
983 struct isl_extent4d phys_level0_sa
;
984 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
987 enum isl_array_pitch_span array_pitch_span
=
988 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
990 struct isl_extent2d phys_slice0_sa
;
991 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
992 &lod_align_sa
, &phys_level0_sa
,
994 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
995 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
997 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1001 const uint32_t array_pitch_sa_rows
=
1002 isl_calc_array_pitch_sa_rows(dev
, info
, dim_layout
, array_pitch_span
,
1003 &lod_align_sa
, &phys_level0_sa
,
1005 assert(array_pitch_sa_rows
% fmtl
->bh
== 0);
1007 const uint32_t array_pitch_el_rows
= array_pitch_sa_rows
/ fmtl
->bh
;
1009 const uint32_t total_h_el
=
1010 isl_calc_total_height_el(dev
, info
, &tile_info
,
1011 phys_level0_sa
.array_len
, row_pitch
,
1012 array_pitch_el_rows
);
1014 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1015 const uint32_t size
= row_pitch
* total_h_sa
;
1017 /* Alignment of surface base address, in bytes */
1018 uint32_t base_alignment
= info
->min_alignment
;
1019 base_alignment
= isl_align(base_alignment
, tile_info
.size
);
1021 *surf
= (struct isl_surf
) {
1023 .dim_layout
= dim_layout
,
1024 .msaa_layout
= msaa_layout
,
1026 .format
= info
->format
,
1028 .levels
= info
->levels
,
1029 .samples
= info
->samples
,
1031 .lod_alignment_el
= lod_align_el
,
1032 .logical_level0_px
= logical_level0_px
,
1033 .phys_level0_sa
= phys_level0_sa
,
1036 .alignment
= base_alignment
,
1037 .row_pitch
= row_pitch
,
1038 .array_pitch_el_rows
= array_pitch_el_rows
,
1039 .array_pitch_span
= array_pitch_span
,
1041 .usage
= info
->usage
,