src/vulkan/isl.h

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file
  26  * @brief Intel Surface Layout
  27  *
  28  * Header Layout
  29  * =============
  30  *
  31  * The header is ordered as:
  32  *    - forward declarations
  33  *    - macros that may be overridden at compile-time for specific gens
  34  *    - enums and constants
  35  *    - structs and unions
  36  *    - functions
  37  *
  38  *
  39  * Surface Units
  40  * =============
  41  *
  42  * Some symbol names have a unit suffix.
  43  *
  44  *    - px: logical pixels
  45  *    - sa: physical surface samples
  46  *    - el: physical surface elements
  47  *    - sa_rows: rows of physical surface samples
  48  *    - el_rows: rows of physical surface elements
  49  *
  50  * The Broadwell PRM [1] defines a surface element as follows:
  51  *
  52  *    An element is defined as a pixel in uncompresed surface formats, and as
  53  *    a compression block in compressed surface formats. For
  54  *    MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample.
  55  *
  56  * [1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >>
  57  *      RENDER_SURFACE_STATE Surface Vertical Alignment (p325)
  58  */
  59
  60 #pragma once
  61
  62 #include <assert.h>
  63 #include <stdbool.h>
  64 #include <stdint.h>
  65
  66 #include "util/macros.h"
  67
  68 #ifdef __cplusplus
  69 extern "C" {
  70 #endif
  71
  72 struct brw_device_info;
  73
  74 #ifndef ISL_DEV_GEN
  75 /**
  76  * @brief Get the hardware generation of isl_device.
  77  *
  78  * You can define this as a compile-time constant in the CFLAGS. For example,
  79  * `gcc -DISL_DEV_GEN(dev)=9 ...`.
  80  */
  81 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
  82 #endif
  83
  84 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
  85 /**
  86  * You can define this as a compile-time constant in the CFLAGS. For example,
  87  * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
  88  */
  89 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
  90 #endif
  91
  92 /**
  93  * Hardware enumeration SURFACE_FORMAT.
  94  *
  95  * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
  96  * Enumerations: SURFACE_FORMAT.
  97  */
  98 enum isl_format {
  99    ISL_FORMAT_R32G32B32A32_FLOAT =                               0,
 100    ISL_FORMAT_R32G32B32A32_SINT =                                1,
 101    ISL_FORMAT_R32G32B32A32_UINT =                                2,
 102    ISL_FORMAT_R32G32B32A32_UNORM =                               3,
 103    ISL_FORMAT_R32G32B32A32_SNORM =                               4,
 104    ISL_FORMAT_R64G64_FLOAT =                                     5,
 105    ISL_FORMAT_R32G32B32X32_FLOAT =                               6,
 106    ISL_FORMAT_R32G32B32A32_SSCALED =                             7,
 107    ISL_FORMAT_R32G32B32A32_USCALED =                             8,
 108    ISL_FORMAT_R32G32B32A32_SFIXED =                             32,
 109    ISL_FORMAT_R64G64_PASSTHRU =                                 33,
 110    ISL_FORMAT_R32G32B32_FLOAT =                                 64,
 111    ISL_FORMAT_R32G32B32_SINT =                                  65,
 112    ISL_FORMAT_R32G32B32_UINT =                                  66,
 113    ISL_FORMAT_R32G32B32_UNORM =                                 67,
 114    ISL_FORMAT_R32G32B32_SNORM =                                 68,
 115    ISL_FORMAT_R32G32B32_SSCALED =                               69,
 116    ISL_FORMAT_R32G32B32_USCALED =                               70,
 117    ISL_FORMAT_R32G32B32_SFIXED =                                80,
 118    ISL_FORMAT_R16G16B16A16_UNORM =                             128,
 119    ISL_FORMAT_R16G16B16A16_SNORM =                             129,
 120    ISL_FORMAT_R16G16B16A16_SINT =                              130,
 121    ISL_FORMAT_R16G16B16A16_UINT =                              131,
 122    ISL_FORMAT_R16G16B16A16_FLOAT =                             132,
 123    ISL_FORMAT_R32G32_FLOAT =                                   133,
 124    ISL_FORMAT_R32G32_SINT =                                    134,
 125    ISL_FORMAT_R32G32_UINT =                                    135,
 126    ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS =                       136,
 127    ISL_FORMAT_X32_TYPELESS_G8X24_UINT =                        137,
 128    ISL_FORMAT_L32A32_FLOAT =                                   138,
 129    ISL_FORMAT_R32G32_UNORM =                                   139,
 130    ISL_FORMAT_R32G32_SNORM =                                   140,
 131    ISL_FORMAT_R64_FLOAT =                                      141,
 132    ISL_FORMAT_R16G16B16X16_UNORM =                             142,
 133    ISL_FORMAT_R16G16B16X16_FLOAT =                             143,
 134    ISL_FORMAT_A32X32_FLOAT =                                   144,
 135    ISL_FORMAT_L32X32_FLOAT =                                   145,
 136    ISL_FORMAT_I32X32_FLOAT =                                   146,
 137    ISL_FORMAT_R16G16B16A16_SSCALED =                           147,
 138    ISL_FORMAT_R16G16B16A16_USCALED =                           148,
 139    ISL_FORMAT_R32G32_SSCALED =                                 149,
 140    ISL_FORMAT_R32G32_USCALED =                                 150,
 141    ISL_FORMAT_R32G32_SFIXED =                                  160,
 142    ISL_FORMAT_R64_PASSTHRU =                                   161,
 143    ISL_FORMAT_B8G8R8A8_UNORM =                                 192,
 144    ISL_FORMAT_B8G8R8A8_UNORM_SRGB =                            193,
 145    ISL_FORMAT_R10G10B10A2_UNORM =                              194,
 146    ISL_FORMAT_R10G10B10A2_UNORM_SRGB =                         195,
 147    ISL_FORMAT_R10G10B10A2_UINT =                               196,
 148    ISL_FORMAT_R10G10B10_SNORM_A2_UNORM =                       197,
 149    ISL_FORMAT_R8G8B8A8_UNORM =                                 199,
 150    ISL_FORMAT_R8G8B8A8_UNORM_SRGB =                            200,
 151    ISL_FORMAT_R8G8B8A8_SNORM =                                 201,
 152    ISL_FORMAT_R8G8B8A8_SINT =                                  202,
 153    ISL_FORMAT_R8G8B8A8_UINT =                                  203,
 154    ISL_FORMAT_R16G16_UNORM =                                   204,
 155    ISL_FORMAT_R16G16_SNORM =                                   205,
 156    ISL_FORMAT_R16G16_SINT =                                    206,
 157    ISL_FORMAT_R16G16_UINT =                                    207,
 158    ISL_FORMAT_R16G16_FLOAT =                                   208,
 159    ISL_FORMAT_B10G10R10A2_UNORM =                              209,
 160    ISL_FORMAT_B10G10R10A2_UNORM_SRGB =                         210,
 161    ISL_FORMAT_R11G11B10_FLOAT =                                211,
 162    ISL_FORMAT_R32_SINT =                                       214,
 163    ISL_FORMAT_R32_UINT =                                       215,
 164    ISL_FORMAT_R32_FLOAT =                                      216,
 165    ISL_FORMAT_R24_UNORM_X8_TYPELESS =                          217,
 166    ISL_FORMAT_X24_TYPELESS_G8_UINT =                           218,
 167    ISL_FORMAT_L32_UNORM =                                      221,
 168    ISL_FORMAT_A32_UNORM =                                      222,
 169    ISL_FORMAT_L16A16_UNORM =                                   223,
 170    ISL_FORMAT_I24X8_UNORM =                                    224,
 171    ISL_FORMAT_L24X8_UNORM =                                    225,
 172    ISL_FORMAT_A24X8_UNORM =                                    226,
 173    ISL_FORMAT_I32_FLOAT =                                      227,
 174    ISL_FORMAT_L32_FLOAT =                                      228,
 175    ISL_FORMAT_A32_FLOAT =                                      229,
 176    ISL_FORMAT_X8B8_UNORM_G8R8_SNORM =                          230,
 177    ISL_FORMAT_A8X8_UNORM_G8R8_SNORM =                          231,
 178    ISL_FORMAT_B8X8_UNORM_G8R8_SNORM =                          232,
 179    ISL_FORMAT_B8G8R8X8_UNORM =                                 233,
 180    ISL_FORMAT_B8G8R8X8_UNORM_SRGB =                            234,
 181    ISL_FORMAT_R8G8B8X8_UNORM =                                 235,
 182    ISL_FORMAT_R8G8B8X8_UNORM_SRGB =                            236,
 183    ISL_FORMAT_R9G9B9E5_SHAREDEXP =                             237,
 184    ISL_FORMAT_B10G10R10X2_UNORM =                              238,
 185    ISL_FORMAT_L16A16_FLOAT =                                   240,
 186    ISL_FORMAT_R32_UNORM =                                      241,
 187    ISL_FORMAT_R32_SNORM =                                      242,
 188    ISL_FORMAT_R10G10B10X2_USCALED =                            243,
 189    ISL_FORMAT_R8G8B8A8_SSCALED =                               244,
 190    ISL_FORMAT_R8G8B8A8_USCALED =                               245,
 191    ISL_FORMAT_R16G16_SSCALED =                                 246,
 192    ISL_FORMAT_R16G16_USCALED =                                 247,
 193    ISL_FORMAT_R32_SSCALED =                                    248,
 194    ISL_FORMAT_R32_USCALED =                                    249,
 195    ISL_FORMAT_B5G6R5_UNORM =                                   256,
 196    ISL_FORMAT_B5G6R5_UNORM_SRGB =                              257,
 197    ISL_FORMAT_B5G5R5A1_UNORM =                                 258,
 198    ISL_FORMAT_B5G5R5A1_UNORM_SRGB =                            259,
 199    ISL_FORMAT_B4G4R4A4_UNORM =                                 260,
 200    ISL_FORMAT_B4G4R4A4_UNORM_SRGB =                            261,
 201    ISL_FORMAT_R8G8_UNORM =                                     262,
 202    ISL_FORMAT_R8G8_SNORM =                                     263,
 203    ISL_FORMAT_R8G8_SINT =                                      264,
 204    ISL_FORMAT_R8G8_UINT =                                      265,
 205    ISL_FORMAT_R16_UNORM =                                      266,
 206    ISL_FORMAT_R16_SNORM =                                      267,
 207    ISL_FORMAT_R16_SINT =                                       268,
 208    ISL_FORMAT_R16_UINT =                                       269,
 209    ISL_FORMAT_R16_FLOAT =                                      270,
 210    ISL_FORMAT_A8P8_UNORM_PALETTE0 =                            271,
 211    ISL_FORMAT_A8P8_UNORM_PALETTE1 =                            272,
 212    ISL_FORMAT_I16_UNORM =                                      273,
 213    ISL_FORMAT_L16_UNORM =                                      274,
 214    ISL_FORMAT_A16_UNORM =                                      275,
 215    ISL_FORMAT_L8A8_UNORM =                                     276,
 216    ISL_FORMAT_I16_FLOAT =                                      277,
 217    ISL_FORMAT_L16_FLOAT =                                      278,
 218    ISL_FORMAT_A16_FLOAT =                                      279,
 219    ISL_FORMAT_L8A8_UNORM_SRGB =                                280,
 220    ISL_FORMAT_R5G5_SNORM_B6_UNORM =                            281,
 221    ISL_FORMAT_B5G5R5X1_UNORM =                                 282,
 222    ISL_FORMAT_B5G5R5X1_UNORM_SRGB =                            283,
 223    ISL_FORMAT_R8G8_SSCALED =                                   284,
 224    ISL_FORMAT_R8G8_USCALED =                                   285,
 225    ISL_FORMAT_R16_SSCALED =                                    286,
 226    ISL_FORMAT_R16_USCALED =                                    287,
 227    ISL_FORMAT_P8A8_UNORM_PALETTE0 =                            290,
 228    ISL_FORMAT_P8A8_UNORM_PALETTE1 =                            291,
 229    ISL_FORMAT_A1B5G5R5_UNORM =                                 292,
 230    ISL_FORMAT_A4B4G4R4_UNORM =                                 293,
 231    ISL_FORMAT_L8A8_UINT =                                      294,
 232    ISL_FORMAT_L8A8_SINT =                                      295,
 233    ISL_FORMAT_R8_UNORM =                                       320,
 234    ISL_FORMAT_R8_SNORM =                                       321,
 235    ISL_FORMAT_R8_SINT =                                        322,
 236    ISL_FORMAT_R8_UINT =                                        323,
 237    ISL_FORMAT_A8_UNORM =                                       324,
 238    ISL_FORMAT_I8_UNORM =                                       325,
 239    ISL_FORMAT_L8_UNORM =                                       326,
 240    ISL_FORMAT_P4A4_UNORM_PALETTE0 =                            327,
 241    ISL_FORMAT_A4P4_UNORM_PALETTE0 =                            328,
 242    ISL_FORMAT_R8_SSCALED =                                     329,
 243    ISL_FORMAT_R8_USCALED =                                     330,
 244    ISL_FORMAT_P8_UNORM_PALETTE0 =                              331,
 245    ISL_FORMAT_L8_UNORM_SRGB =                                  332,
 246    ISL_FORMAT_P8_UNORM_PALETTE1 =                              333,
 247    ISL_FORMAT_P4A4_UNORM_PALETTE1 =                            334,
 248    ISL_FORMAT_A4P4_UNORM_PALETTE1 =                            335,
 249    ISL_FORMAT_Y8_UNORM =                                       336,
 250    ISL_FORMAT_L8_UINT =                                        338,
 251    ISL_FORMAT_L8_SINT =                                        339,
 252    ISL_FORMAT_I8_UINT =                                        340,
 253    ISL_FORMAT_I8_SINT =                                        341,
 254    ISL_FORMAT_DXT1_RGB_SRGB =                                  384,
 255    ISL_FORMAT_R1_UNORM =                                       385,
 256    ISL_FORMAT_YCRCB_NORMAL =                                   386,
 257    ISL_FORMAT_YCRCB_SWAPUVY =                                  387,
 258    ISL_FORMAT_P2_UNORM_PALETTE0 =                              388,
 259    ISL_FORMAT_P2_UNORM_PALETTE1 =                              389,
 260    ISL_FORMAT_BC1_UNORM =                                      390,
 261    ISL_FORMAT_BC2_UNORM =                                      391,
 262    ISL_FORMAT_BC3_UNORM =                                      392,
 263    ISL_FORMAT_BC4_UNORM =                                      393,
 264    ISL_FORMAT_BC5_UNORM =                                      394,
 265    ISL_FORMAT_BC1_UNORM_SRGB =                                 395,
 266    ISL_FORMAT_BC2_UNORM_SRGB =                                 396,
 267    ISL_FORMAT_BC3_UNORM_SRGB =                                 397,
 268    ISL_FORMAT_MONO8 =                                          398,
 269    ISL_FORMAT_YCRCB_SWAPUV =                                   399,
 270    ISL_FORMAT_YCRCB_SWAPY =                                    400,
 271    ISL_FORMAT_DXT1_RGB =                                       401,
 272    ISL_FORMAT_FXT1 =                                           402,
 273    ISL_FORMAT_R8G8B8_UNORM =                                   403,
 274    ISL_FORMAT_R8G8B8_SNORM =                                   404,
 275    ISL_FORMAT_R8G8B8_SSCALED =                                 405,
 276    ISL_FORMAT_R8G8B8_USCALED =                                 406,
 277    ISL_FORMAT_R64G64B64A64_FLOAT =                             407,
 278    ISL_FORMAT_R64G64B64_FLOAT =                                408,
 279    ISL_FORMAT_BC4_SNORM =                                      409,
 280    ISL_FORMAT_BC5_SNORM =                                      410,
 281    ISL_FORMAT_R16G16B16_FLOAT =                                411,
 282    ISL_FORMAT_R16G16B16_UNORM =                                412,
 283    ISL_FORMAT_R16G16B16_SNORM =                                413,
 284    ISL_FORMAT_R16G16B16_SSCALED =                              414,
 285    ISL_FORMAT_R16G16B16_USCALED =                              415,
 286    ISL_FORMAT_BC6H_SF16 =                                      417,
 287    ISL_FORMAT_BC7_UNORM =                                      418,
 288    ISL_FORMAT_BC7_UNORM_SRGB =                                 419,
 289    ISL_FORMAT_BC6H_UF16 =                                      420,
 290    ISL_FORMAT_PLANAR_420_8 =                                   421,
 291    ISL_FORMAT_R8G8B8_UNORM_SRGB =                              424,
 292    ISL_FORMAT_ETC1_RGB8 =                                      425,
 293    ISL_FORMAT_ETC2_RGB8 =                                      426,
 294    ISL_FORMAT_EAC_R11 =                                        427,
 295    ISL_FORMAT_EAC_RG11 =                                       428,
 296    ISL_FORMAT_EAC_SIGNED_R11 =                                 429,
 297    ISL_FORMAT_EAC_SIGNED_RG11 =                                430,
 298    ISL_FORMAT_ETC2_SRGB8 =                                     431,
 299    ISL_FORMAT_R16G16B16_UINT =                                 432,
 300    ISL_FORMAT_R16G16B16_SINT =                                 433,
 301    ISL_FORMAT_R32_SFIXED =                                     434,
 302    ISL_FORMAT_R10G10B10A2_SNORM =                              435,
 303    ISL_FORMAT_R10G10B10A2_USCALED =                            436,
 304    ISL_FORMAT_R10G10B10A2_SSCALED =                            437,
 305    ISL_FORMAT_R10G10B10A2_SINT =                               438,
 306    ISL_FORMAT_B10G10R10A2_SNORM =                              439,
 307    ISL_FORMAT_B10G10R10A2_USCALED =                            440,
 308    ISL_FORMAT_B10G10R10A2_SSCALED =                            441,
 309    ISL_FORMAT_B10G10R10A2_UINT =                               442,
 310    ISL_FORMAT_B10G10R10A2_SINT =                               443,
 311    ISL_FORMAT_R64G64B64A64_PASSTHRU =                          444,
 312    ISL_FORMAT_R64G64B64_PASSTHRU =                             445,
 313    ISL_FORMAT_ETC2_RGB8_PTA =                                  448,
 314    ISL_FORMAT_ETC2_SRGB8_PTA =                                 449,
 315    ISL_FORMAT_ETC2_EAC_RGBA8 =                                 450,
 316    ISL_FORMAT_ETC2_EAC_SRGB8_A8 =                              451,
 317    ISL_FORMAT_R8G8B8_UINT =                                    456,
 318    ISL_FORMAT_R8G8B8_SINT =                                    457,
 319    ISL_FORMAT_RAW =                                            511,
 320
 321    /* Hardware doesn't understand this out-of-band value */
 322    ISL_FORMAT_UNSUPPORTED =                             UINT16_MAX,
 323 };
 324
 325 /**
 326  * Numerical base type for channels of isl_format.
 327  */
 328 enum isl_base_type {
 329    ISL_VOID,
 330    ISL_RAW,
 331    ISL_UNORM,
 332    ISL_SNORM,
 333    ISL_UFLOAT,
 334    ISL_SFLOAT,
 335    ISL_UFIXED,
 336    ISL_SFIXED,
 337    ISL_UINT,
 338    ISL_SINT,
 339    ISL_USCALED,
 340    ISL_SSCALED,
 341 };
 342
 343 /**
 344  * Colorspace of isl_format.
 345  */
 346 enum isl_colorspace {
 347    ISL_COLORSPACE_NONE = 0,
 348    ISL_COLORSPACE_LINEAR,
 349    ISL_COLORSPACE_SRGB,
 350    ISL_COLORSPACE_YUV,
 351 };
 352
 353 /**
 354  * Texture compression mode of isl_format.
 355  */
 356 enum isl_txc {
 357    ISL_TXC_NONE = 0,
 358    ISL_TXC_DXT1,
 359    ISL_TXC_DXT3,
 360    ISL_TXC_DXT5,
 361    ISL_TXC_FXT1,
 362    ISL_TXC_RGTC1,
 363    ISL_TXC_RGTC2,
 364    ISL_TXC_BPTC,
 365    ISL_TXC_ETC1,
 366    ISL_TXC_ETC2,
 367 };
 368
 369 /**
 370  * @brief Hardware tile mode
 371  *
 372  * WARNING: These values differ from the hardware enum values, which are
 373  * unstable across hardware generations.
 374  *
 375  * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
 376  * clearly distinguish it from Yf and Ys.
 377  */
 378 enum isl_tiling {
 379    ISL_TILING_LINEAR = 0,
 380    ISL_TILING_W,
 381    ISL_TILING_X,
 382    ISL_TILING_Y0, /**< Legacy Y tiling */
 383    ISL_TILING_Yf,
 384    ISL_TILING_Ys,
 385 };
 386
 387 /**
 388  * @defgroup Tiling Flags
 389  * @{
 390  */
 391 typedef uint32_t isl_tiling_flags_t;
 392 #define ISL_TILING_LINEAR_BIT             (1u << ISL_TILING_LINEAR)
 393 #define ISL_TILING_W_BIT                  (1u << ISL_TILING_W)
 394 #define ISL_TILING_X_BIT                  (1u << ISL_TILING_X)
 395 #define ISL_TILING_Y0_BIT                 (1u << ISL_TILING_Y0)
 396 #define ISL_TILING_Yf_BIT                 (1u << ISL_TILING_Yf)
 397 #define ISL_TILING_Ys_BIT                 (1u << ISL_TILING_Ys)
 398 #define ISL_TILING_ANY_MASK               (~0u)
 399 #define ISL_TILING_NON_LINEAR_MASK        (~ISL_TILING_LINEAR_BIT)
 400
 401 /** Any Y tiling, including legacy Y tiling. */
 402 #define ISL_TILING_ANY_Y_MASK             (ISL_TILING_Y0_BIT | \
 403                                            ISL_TILING_Yf_BIT | \
 404                                            ISL_TILING_Ys_BIT)
 405
 406 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
 407 #define ISL_TILING_STD_Y_MASK             (ISL_TILING_Yf_BIT | \
 408                                            ISL_TILING_Ys_BIT)
 409 /** @} */
 410
 411 /**
 412  * @brief Logical dimension of surface.
 413  *
 414  * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
 415  * as 2D array surfaces.
 416  */
 417 enum isl_surf_dim {
 418    ISL_SURF_DIM_1D,
 419    ISL_SURF_DIM_2D,
 420    ISL_SURF_DIM_3D,
 421 };
 422
 423 /**
 424  * @brief Physical layout of the surface's dimensions.
 425  */
 426 enum isl_dim_layout {
 427    /**
 428     * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
 429     * 6.17.3: 2D Surfaces.
 430     *
 431     * On many gens, 1D surfaces share the same layout as 2D surfaces.  From
 432     * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
 433     *
 434     *    One-dimensional surfaces are identical to 2D surfaces with height of
 435     *    one.
 436     */
 437    ISL_DIM_LAYOUT_GEN4_2D,
 438
 439    /**
 440     * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
 441     * 6.17.5: 3D Surfaces.
 442     */
 443    ISL_DIM_LAYOUT_GEN4_3D,
 444
 445    /**
 446     * For details, see the Skylake BSpec >> Memory Views >> Common Surface
 447     * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
 448     */
 449    ISL_DIM_LAYOUT_GEN9_1D,
 450 };
 451
 452 /* TODO(chadv): Explain */
 453 enum isl_array_pitch_span {
 454    ISL_ARRAY_PITCH_SPAN_FULL,
 455    ISL_ARRAY_PITCH_SPAN_COMPACT,
 456 };
 457
 458 /**
 459  * @defgroup Surface Usage
 460  * @{
 461  */
 462 typedef uint64_t isl_surf_usage_flags_t;
 463 #define ISL_SURF_USAGE_RENDER_TARGET_BIT       (1u << 0)
 464 #define ISL_SURF_USAGE_DEPTH_BIT               (1u << 1)
 465 #define ISL_SURF_USAGE_STENCIL_BIT             (1u << 2)
 466 #define ISL_SURF_USAGE_TEXTURE_BIT             (1u << 3)
 467 #define ISL_SURF_USAGE_CUBE_BIT                (1u << 4)
 468 #define ISL_SURF_USAGE_DISABLE_AUX_BIT         (1u << 5)
 469 #define ISL_SURF_USAGE_DISPLAY_BIT             (1u << 6)
 470 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT   (1u << 7)
 471 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT  (1u << 8)
 472 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT  (1u << 9)
 473 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT      (1u << 10)
 474 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT      (1u << 11)
 475 /** @} */
 476
 477 /**
 478  * @brief Multisample Format
 479  */
 480 enum isl_msaa_layout {
 481    /**
 482     * @brief Suface is single-sampled.
 483     */
 484    ISL_MSAA_LAYOUT_NONE,
 485
 486    /**
 487     * @brief [SNB+] Interleaved Multisample Format
 488     *
 489     * In this format, multiple samples are interleaved into each cacheline.
 490     * In other words, the sample index is swizzled into the low 6 bits of the
 491     * surface's virtual address space.
 492     *
 493     * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
 494     * and its pixel format is 32bpp. Then the first cacheline is arranged
 495     * thus:
 496     *
 497     *    (0,0,0) (0,1,0)   (0,0,1) (1,0,1)
 498     *    (1,0,0) (1,1,0)   (0,1,1) (1,1,1)
 499     *
 500     *    (0,0,2) (1,0,2)   (0,0,3) (1,0,3)
 501     *    (0,1,2) (1,1,2)   (0,1,3) (1,1,3)
 502     *
 503     * The hardware docs refer to this format with multiple terms.  In
 504     * Sandybridge, this is the only multisample format; so no term is used.
 505     * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
 506     * Multisample Surface). Later hardware docs additionally refer to this
 507     * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
 508     * color surfaces).
 509     *
 510     * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
 511     * Surface Behavior".
 512     *
 513     * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
 514     * Multisampled Surfaces".
 515     */
 516    ISL_MSAA_LAYOUT_INTERLEAVED,
 517
 518    /**
 519     * @brief [IVB+] Array Multisample Format
 520     *
 521     * In this format, the surface's physical layout resembles that of a
 522     * 2D array surface.
 523     *
 524     * Suppose the multisample surface's logical extent is (w, h) and its
 525     * sample count is N. Then surface's physical extent is the same as
 526     * a singlesample 2D surface whose logical extent is (w, h) and array
 527     * length is N.  Array slice `i` contains the pixel values for sample
 528     * index `i`.
 529     *
 530     * The Ivybridge docs refer to surfaces in this format as UMS
 531     * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
 532     * Surface). The Broadwell docs additionally refer to this format as
 533     * MSFMT_MSS (MSS=Multisample Surface Storage).
 534     *
 535     * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
 536     * Multisample Surfaces".
 537     *
 538     * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
 539     * Multisample Surfaces".
 540     */
 541    ISL_MSAA_LAYOUT_ARRAY,
 542 };
 543
 544
 545 struct isl_device {
 546    const struct brw_device_info *info;
 547    bool use_separate_stencil;
 548 };
 549
 550 struct isl_extent2d {
 551    union { uint32_t w, width; };
 552    union { uint32_t h, height; };
 553 };
 554
 555 struct isl_extent3d {
 556    union { uint32_t w, width; };
 557    union { uint32_t h, height; };
 558    union { uint32_t d, depth; };
 559 };
 560
 561 struct isl_extent4d {
 562    union { uint32_t w, width; };
 563    union { uint32_t h, height; };
 564    union { uint32_t d, depth; };
 565    union { uint32_t a, array_len; };
 566 };
 567
 568 struct isl_channel_layout {
 569    enum isl_base_type type;
 570    uint8_t bits; /**< Size in bits */
 571 };
 572
 573 struct isl_format_layout {
 574    enum isl_format format;
 575
 576    uint16_t bpb; /**< Bits per block */
 577    uint8_t bs; /**< Block size, in bytes, rounded towards 0 */
 578    uint8_t bw; /**< Block width, in pixels */
 579    uint8_t bh; /**< Block height, in pixels */
 580    uint8_t bd; /**< Block depth, in pixels */
 581
 582    struct {
 583       struct isl_channel_layout r; /**< Red channel */
 584       struct isl_channel_layout g; /**< Green channel */
 585       struct isl_channel_layout b; /**< Blue channel */
 586       struct isl_channel_layout a; /**< Alpha channel */
 587       struct isl_channel_layout l; /**< Luminance channel */
 588       struct isl_channel_layout i; /**< Intensity channel */
 589       struct isl_channel_layout p; /**< Palette channel */
 590    } channels;
 591
 592    enum isl_colorspace colorspace;
 593    enum isl_txc txc;
 594 };
 595
 596 struct isl_tile_info {
 597    enum isl_tiling tiling;
 598    uint32_t width; /**< in bytes */
 599    uint32_t height; /**< in rows of memory */
 600    uint32_t size; /**< in bytes */
 601 };
 602
 603 /**
 604  * @brief Input to surface initialization
 605  *
 606  * @invariant width >= 1
 607  * @invariant height >= 1
 608  * @invariant depth >= 1
 609  * @invariant levels >= 1
 610  * @invariant samples >= 1
 611  * @invariant array_len >= 1
 612  *
 613  * @invariant if 1D then height == 1 and depth == 1 and samples == 1
 614  * @invariant if 2D then depth == 1
 615  * @invariant if 3D then array_len == 1 and samples == 1
 616  */
 617 struct isl_surf_init_info {
 618    enum isl_surf_dim dim;
 619    enum isl_format format;
 620
 621    uint32_t width;
 622    uint32_t height;
 623    uint32_t depth;
 624    uint32_t levels;
 625    uint32_t array_len;
 626    uint32_t samples;
 627
 628    /** Lower bound for isl_surf::alignment, in bytes. */
 629    uint32_t min_alignment;
 630
 631    /** Lower bound for isl_surf::pitch, in bytes. */
 632    uint32_t min_pitch;
 633
 634    isl_surf_usage_flags_t usage;
 635
 636    /** Flags that alter how ISL selects isl_surf::tiling.  */
 637    isl_tiling_flags_t tiling_flags;
 638 };
 639
 640 struct isl_surf {
 641    enum isl_surf_dim dim;
 642    enum isl_dim_layout dim_layout;
 643    enum isl_msaa_layout msaa_layout;
 644    enum isl_tiling tiling;
 645    enum isl_format format;
 646
 647    /**
 648     * Alignment of the upper-left sample of each LOD, in units of surface
 649     * elements.
 650     */
 651    struct isl_extent3d lod_alignment_el;
 652
 653    /**
 654     * Logical extent of the surface's base level, in units of pixels.  This is
 655     * identical to the extent defined in isl_surf_init_info.
 656     */
 657    struct isl_extent4d logical_level0_px;
 658
 659    /**
 660     * Physical extent of the surface's base level, in units of pixels.
 661     *
 662     * Consider isl_dim_layout as an operator that transforms a logical surface
 663     * layout to a physical surface layout. Then
 664     *
 665     *    logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
 666     *    isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
 667     */
 668    struct isl_extent4d phys_level0_sa;
 669
 670    uint32_t levels;
 671    uint32_t samples;
 672
 673    /** Total size of the surface, in bytes. */
 674    uint32_t size;
 675
 676    /** Required alignment for the surface's base address. */
 677    uint32_t alignment;
 678
 679    /**
 680     * Pitch between vertically adjacent samples, in bytes.
 681     */
 682    uint32_t row_pitch;
 683
 684    /**
 685     * Pitch between physical array slices, in rows of surface elements.
 686     */
 687    uint32_t array_pitch_el_rows;
 688
 689    enum isl_array_pitch_span array_pitch_span;
 690
 691    /** Copy of isl_surf_init_info::usage. */
 692    isl_surf_usage_flags_t usage;
 693 };
 694
 695 extern const struct isl_format_layout isl_format_layouts[];
 696
 697 void
 698 isl_device_init(struct isl_device *dev,
 699                 const struct brw_device_info *info);
 700
 701 static inline const struct isl_format_layout * ATTRIBUTE_CONST
 702 isl_format_get_layout(enum isl_format fmt)
 703 {
 704    return &isl_format_layouts[fmt];
 705 }
 706
 707 bool
 708 isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 709
 710 static inline bool
 711 isl_format_is_compressed(enum isl_format fmt)
 712 {
 713    const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
 714
 715    return fmtl->txc != ISL_TXC_NONE;
 716 }
 717
 718 static inline bool
 719 isl_format_has_bc_compression(enum isl_format fmt)
 720 {
 721    switch (isl_format_get_layout(fmt)->txc) {
 722    case ISL_TXC_DXT1:
 723    case ISL_TXC_DXT3:
 724    case ISL_TXC_DXT5:
 725       return true;
 726    case ISL_TXC_NONE:
 727    case ISL_TXC_FXT1:
 728    case ISL_TXC_RGTC1:
 729    case ISL_TXC_RGTC2:
 730    case ISL_TXC_BPTC:
 731    case ISL_TXC_ETC1:
 732    case ISL_TXC_ETC2:
 733       return false;
 734    }
 735
 736    unreachable("bad texture compression mode");
 737    return false;
 738 }
 739
 740 static inline bool
 741 isl_format_is_yuv(enum isl_format fmt)
 742 {
 743    const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
 744
 745    return fmtl->colorspace == ISL_COLORSPACE_YUV;
 746 }
 747
 748 static inline bool
 749 isl_format_block_is_1x1x1(enum isl_format fmt)
 750 {
 751    const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
 752
 753    return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
 754 }
 755
 756 static inline bool
 757 isl_tiling_is_std_y(enum isl_tiling tiling)
 758 {
 759    return (1u << tiling) & ISL_TILING_STD_Y_MASK;
 760 }
 761
 762 bool
 763 isl_tiling_get_info(const struct isl_device *dev,
 764                     enum isl_tiling tiling,
 765                     uint32_t format_block_size,
 766                     struct isl_tile_info *info);
 767
 768 void
 769 isl_tiling_get_extent(const struct isl_device *dev,
 770                       enum isl_tiling tiling,
 771                       uint32_t format_block_size,
 772                       struct isl_extent2d *e);
 773 bool
 774 isl_surf_choose_tiling(const struct isl_device *dev,
 775                        const struct isl_surf_init_info *restrict info,
 776                        enum isl_tiling *tiling);
 777
 778 static inline bool
 779 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
 780 {
 781    return usage & ISL_SURF_USAGE_DISPLAY_BIT;
 782 }
 783
 784 static inline bool
 785 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
 786 {
 787    return usage & ISL_SURF_USAGE_DEPTH_BIT;
 788 }
 789
 790 static inline bool
 791 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
 792 {
 793    return usage & ISL_SURF_USAGE_STENCIL_BIT;
 794 }
 795
 796 static inline bool
 797 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
 798 {
 799    return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
 800           (usage & ISL_SURF_USAGE_STENCIL_BIT);
 801 }
 802
 803 static inline bool
 804 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
 805 {
 806    return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
 807 }
 808
 809 static inline bool
 810 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
 811 {
 812    return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
 813           (info->format == ISL_FORMAT_R16_UNORM);
 814 }
 815
 816 static inline bool
 817 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
 818 {
 819    return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
 820           (info->format == ISL_FORMAT_R32_FLOAT);
 821 }
 822
 823 static inline struct isl_extent2d
 824 isl_extent2d(uint32_t width, uint32_t height)
 825 {
 826    return (struct isl_extent2d) { .w = width, .h = height };
 827 }
 828
 829 static inline struct isl_extent3d
 830 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
 831 {
 832    return (struct isl_extent3d) { .w = width, .h = height, .d = depth };
 833 }
 834
 835 static inline struct isl_extent4d
 836 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
 837              uint32_t array_len)
 838 {
 839    return (struct isl_extent4d) {
 840       .w = width,
 841       .h = height,
 842       .d = depth,
 843       .a = array_len,
 844    };
 845 }
 846
 847 #define isl_surf_init(dev, surf, ...) \
 848    isl_surf_init_s((dev), (surf), \
 849                    &(struct isl_surf_init_info) {  __VA_ARGS__ });
 850
 851 bool
 852 isl_surf_init_s(const struct isl_device *dev,
 853                 struct isl_surf *surf,
 854                 const struct isl_surf_init_info *restrict info);
 855
 856 /**
 857  * Alignment of the upper-left sample of each LOD, in units of surface
 858  * elements.
 859  */
 860 static inline struct isl_extent3d
 861 isl_surf_get_lod_alignment_el(const struct isl_surf *surf)
 862 {
 863    return surf->lod_alignment_el;
 864 }
 865
 866 /**
 867  * Alignment of the upper-left sample of each LOD, in units of surface
 868  * samples.
 869  */
 870 static inline struct isl_extent3d
 871 isl_surf_get_lod_alignment_sa(const struct isl_surf *surf)
 872 {
 873    const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
 874
 875    return (struct isl_extent3d) {
 876       .w = fmtl->bw * surf->lod_alignment_el.w,
 877       .h = fmtl->bh * surf->lod_alignment_el.h,
 878       .d = fmtl->bd * surf->lod_alignment_el.d,
 879    };
 880 }
 881
 882 /**
 883  * Pitch between physical array slices, in rows of surface elements.
 884  */
 885 static inline uint32_t
 886 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
 887 {
 888    return surf->array_pitch_el_rows;
 889 }
 890
 891 /**
 892  * Pitch between physical array slices, in rows of surface samples.
 893  */
 894 static inline uint32_t
 895 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
 896 {
 897    const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
 898    return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
 899 }
 900
 901 /**
 902  * Pitch between physical array slices, in bytes.
 903  */
 904 static inline uint32_t
 905 isl_surf_get_array_pitch(const struct isl_surf *surf)
 906 {
 907    return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
 908 }
 909
 910 #ifdef __cplusplus
 911 }
 912 #endif