src/vulkan/isl_gen7.c

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include "isl_gen7.h"
  25 #include "isl_priv.h"
  26
  27 bool
  28 gen7_choose_msaa_layout(const struct isl_device *dev,
  29                         const struct isl_surf_init_info *info,
  30                         enum isl_tiling tiling,
  31                         enum isl_msaa_layout *msaa_layout)
  32 {
  33    const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
  34
  35    bool require_array = false;
  36    bool require_interleaved = false;
  37
  38    assert(ISL_DEV_GEN(dev) == 7);
  39    assert(info->samples >= 1);
  40
  41    if (info->samples == 1) {
  42       *msaa_layout = ISL_MSAA_LAYOUT_NONE;
  43       return true;
  44    }
  45
  46    /* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface
  47     * Format:
  48     *
  49     *    If Number of Multisamples is set to a value other than
  50     *    MULTISAMPLECOUNT_1, this field cannot be set to the following
  51     *    formats: any format with greater than 64 bits per element, any
  52     *    compressed texture format (BC*), and any YCRCB* format.
  53     */
  54    if (fmtl->bs > 8)
  55       return false;
  56    if (isl_format_is_compressed(info->format))
  57       return false;
  58    if (isl_format_is_yuv(info->format))
  59       return false;
  60
  61    /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
  62     * Multisamples:
  63     *
  64     *    - If this field is any value other than MULTISAMPLECOUNT_1, the
  65     *      Surface Type must be SURFTYPE_2D.
  66     *
  67     *    - If this field is any value other than MULTISAMPLECOUNT_1, Surface
  68     *      Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero
  69     */
  70    if (info->dim != ISL_SURF_DIM_2D)
  71       return false;
  72    if (info->levels > 1)
  73       return false;
  74
  75    /* The Ivyrbridge PRM insists twice that signed integer formats cannot be
  76     * multisampled.
  77     *
  78     * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
  79     * Multisamples:
  80     *
  81     *    - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
  82     *      all RT channels are not written.
  83     *
  84     * And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
  85     * RENDER_SURFACE_STATE, MCS Enable:
  86     *
  87     *   This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
  88     *   when all RT channels are not written.
  89     *
  90     * Note that the above SINT restrictions apply only to *MSRTs* (that is,
  91     * *multisampled* render targets). The restrictions seem to permit an MCS
  92     * if the render target is singlesampled.
  93     */
  94    if (isl_format_has_sint_channel(info->format))
  95       return false;
  96
  97    /* More obvious restrictions */
  98    if (isl_surf_usage_is_display(info->usage))
  99       return false;
 100    if (tiling == ISL_TILING_LINEAR)
 101       return false;
 102
 103    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 104     * Suface Storage Format:
 105     *
 106     *    +---------------------+----------------------------------------------------------------+
 107     *    | MSFMT_MSS           | Multsampled surface was/is rendered as a render target         |
 108     *    | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer |
 109     *    +---------------------+----------------------------------------------------------------+
 110     *
 111     * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and
 112     * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED.
 113     */
 114    if (isl_surf_usage_is_depth_or_stencil(info->usage))
 115       require_interleaved = true;
 116
 117    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 118     * Suface Storage Format:
 119     *
 120     *    If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 121     *    is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 122     *    field must be set to MSFMT_MSS.
 123     */
 124    if (info->samples == 8 && info->width == 8192)
 125       require_array = true;
 126
 127    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 128     * Suface Storage Format:
 129     *
 130     *    If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 131     *    ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number
 132     *    of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is
 133     *    > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.
 134     */
 135    if ((info->samples == 8 && info->height > 4194304u) ||
 136        (info->samples == 4 && info->height > 8388608u))
 137       require_interleaved = true;
 138
 139    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 140     * Suface Storage Format:
 141     *
 142     *    This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is
 143     *    one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 144     *    R24_UNORM_X8_TYPELESS.
 145     */
 146    if (info->format == ISL_FORMAT_I24X8_UNORM ||
 147        info->format == ISL_FORMAT_L24X8_UNORM ||
 148        info->format == ISL_FORMAT_A24X8_UNORM ||
 149        info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS)
 150       require_interleaved = true;
 151
 152    if (require_array && require_interleaved)
 153       return false;
 154
 155    if (require_interleaved) {
 156       *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
 157       return true;
 158    }
 159
 160    /* Default to the array layout because it permits multisample
 161     * compression.
 162     */
 163    *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
 164    return true;
 165 }
 166
 167 static bool
 168 gen7_format_needs_valign2(const struct isl_device *dev,
 169                           enum isl_format format)
 170 {
 171    /* This workaround applies only to gen7 */
 172    if (ISL_DEV_GEN(dev) > 7)
 173       return false;
 174
 175    /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
 176     * RENDER_SURFACE_STATE Surface Vertical Alignment:
 177     *
 178     *    - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
 179     *      (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
 180     *      (0x190)
 181     *
 182     *    - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
 183     */
 184    return isl_format_is_yuv(format) ||
 185           format == ISL_FORMAT_R32G32B32_FLOAT;
 186 }
 187
 188 void
 189 gen7_filter_tiling(const struct isl_device *dev,
 190                    const struct isl_surf_init_info *restrict info,
 191                    isl_tiling_flags_t *flags)
 192 {
 193    /* IVB+ requires separate stencil */
 194    assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
 195
 196    /* Clear flags unsupported on this hardware */
 197    if (ISL_DEV_GEN(dev) < 9) {
 198       *flags &= ~ISL_TILING_Yf_BIT;
 199       *flags &= ~ISL_TILING_Ys_BIT;
 200    }
 201
 202    /* And... clear the Yf and Ys bits anyway because Anvil doesn't support
 203     * them yet.
 204     */
 205    *flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */
 206    *flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */
 207
 208    if (isl_surf_usage_is_depth(info->usage)) {
 209       /* Depth requires Y. */
 210       *flags &= ISL_TILING_ANY_Y_MASK;
 211    }
 212
 213    /* Separate stencil requires W tiling, and W tiling requires separate
 214     * stencil.
 215     */
 216    if (isl_surf_usage_is_stencil(info->usage)) {
 217       *flags &= ISL_TILING_W_BIT;
 218    } else {
 219       *flags &= ~ISL_TILING_W_BIT;
 220    }
 221
 222    if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
 223                       ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
 224                       ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
 225       assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
 226       isl_finishme("%s:%s: handle rotated display surfaces",
 227                    __FILE__, __func__);
 228    }
 229
 230    if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
 231                       ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
 232       assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
 233       isl_finishme("%s:%s: handle flipped display surfaces",
 234                    __FILE__, __func__);
 235    }
 236
 237    if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
 238       /* Before Skylake, the display engine does not accept Y */
 239       /* FINISHME[SKL]: Y tiling for display surfaces */
 240       *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
 241    }
 242
 243    if (info->samples > 1) {
 244       /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled
 245        * Surface:
 246        *
 247        *   For multisample render targets, this field must be 1 (true). MSRTs
 248        *   can only be tiled.
 249        *
 250        * Multisample surfaces never require X tiling, and Y tiling generally
 251        * performs better than X. So choose Y. (Unless it's stencil, then it
 252        * must be W).
 253        */
 254       *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT);
 255    }
 256
 257    /* For 1D surfaces, use linear when possible. 1D surfaces (array and
 258     * non-array) do not benefit from tiling. In fact, it leads to less
 259     * efficient use of memory due to tile alignment.
 260     */
 261    if (info->dim == ISL_SURF_DIM_1D && (*flags & ISL_TILING_LINEAR_BIT)) {
 262       *flags = ISL_TILING_LINEAR_BIT;
 263    }
 264
 265    /* workaround */
 266    if (ISL_DEV_GEN(dev) == 7 &&
 267        gen7_format_needs_valign2(dev, info->format) &&
 268        (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 269        info->samples == 1) {
 270       /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
 271        * SURFACE_STATE Surface Vertical Alignment:
 272        *
 273        *     This field must be set to VALIGN_4 for all tiled Y Render Target
 274        *     surfaces.
 275        */
 276       *flags &= ~ISL_TILING_Y0_BIT;
 277    }
 278 }
 279
 280 /**
 281  * Choose horizontal LOD alignment, in units of surface elements.
 282  */
 283 static uint32_t
 284 gen7_choose_halign_el(const struct isl_device *dev,
 285                       const struct isl_surf_init_info *restrict info)
 286 {
 287    if (isl_format_is_compressed(info->format))
 288       return 1;
 289
 290    /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
 291     * RENDER_SURFACE_STATE Surface Hoizontal Alignment:
 292     *
 293     *    - This field is intended to be set to HALIGN_8 only if the surface
 294     *      was rendered as a depth buffer with Z16 format or a stencil buffer,
 295     *      since these surfaces support only alignment of 8. Use of HALIGN_8
 296     *      for other surfaces is supported, but uses more memory.
 297     */
 298    if (isl_surf_info_is_z16(info) ||
 299        isl_surf_usage_is_stencil(info->usage))
 300       return 8;
 301
 302    return 4;
 303 }
 304
 305 /**
 306  * Choose vertical LOD alignment, in units of surface elements.
 307  */
 308 static uint32_t
 309 gen7_choose_valign_el(const struct isl_device *dev,
 310                       const struct isl_surf_init_info *restrict info,
 311                       enum isl_tiling tiling)
 312 {
 313    bool require_valign2 = false;
 314    bool require_valign4 = false;
 315
 316    if (isl_format_is_compressed(info->format))
 317       return 1;
 318
 319    if (gen7_format_needs_valign2(dev, info->format))
 320       require_valign2 = true;
 321
 322    /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1:
 323     * RENDER_SURFACE_STATE Surface Vertical Alignment:
 324     *
 325     *    - This field is intended to be set to VALIGN_4 if the surface was
 326     *      rendered as a depth buffer, for a multisampled (4x) render target,
 327     *      or for a multisampled (8x) render target, since these surfaces
 328     *      support only alignment of 4.  Use of VALIGN_4 for other surfaces is
 329     *      supported, but uses more memory.  This field must be set to
 330     *      VALIGN_4 for all tiled Y Render Target surfaces.
 331     *
 332     */
 333    if (isl_surf_usage_is_depth(info->usage) ||
 334        info->samples > 1 ||
 335        tiling == ISL_TILING_Y0) {
 336       require_valign4 = true;
 337    }
 338
 339    if (isl_surf_usage_is_stencil(info->usage)) {
 340       /* The Ivybridge PRM states that the stencil buffer's vertical alignment
 341        * is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment
 342        * Unit Size]. However, valign=8 is outside the set of valid values of
 343        * RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2
 344        * (0x0) and VALIGN_4 (0x1).
 345        *
 346        * The PRM is generally confused about the width, height, and alignment
 347        * of the stencil buffer; and this confusion appears elsewhere. For
 348        * example, the following PRM text effectively converts the stencil
 349        * buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM,
 350        * Volume 1, Part 1, Section
 351        * 6.18.4.2 Base Address and LOD Calculation]:
 352        *
 353        *    For separate stencil buffer, the width must be mutiplied by 2 and
 354        *    height divided by 2 as follows:
 355        *
 356        *       w_L = 2*i*ceil(W_L/i)
 357        *       h_L = 1/2*j*ceil(H_L/j)
 358        *
 359        * The root of the confusion is that, in W tiling, each pair of rows is
 360        * interleaved into one.
 361        *
 362        * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API
 363        * is more polished.
 364        */
 365       require_valign4 = true;
 366    }
 367
 368    assert(!require_valign2 || !require_valign4);
 369
 370    if (require_valign4)
 371       return 4;
 372
 373    /* Prefer VALIGN_2 because it conserves memory. */
 374    return 2;
 375 }
 376
 377 void
 378 gen7_choose_lod_alignment_el(const struct isl_device *dev,
 379                              const struct isl_surf_init_info *restrict info,
 380                              enum isl_tiling tiling,
 381                              enum isl_msaa_layout msaa_layout,
 382                              struct isl_extent3d *lod_align_el)
 383 {
 384    /* IVB+ does not support combined depthstencil. */
 385    assert(!isl_surf_usage_is_depth_and_stencil(info->usage));
 386
 387    *lod_align_el = (struct isl_extent3d) {
 388       .w = gen7_choose_halign_el(dev, info),
 389       .h = gen7_choose_valign_el(dev, info, tiling),
 390       .d = 1,
 391    };
 392 }