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29 * Calculate the LOD alignment, in units of surface samples, for the standard
30 * tiling formats Yf and Ys.
33 gen9_calc_std_lod_alignment_sa(const struct isl_device
*dev
,
34 const struct isl_surf_init_info
*restrict info
,
35 enum isl_tiling tiling
,
36 enum isl_msaa_layout msaa_layout
,
37 struct isl_extent3d
*align_sa
)
39 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
41 assert(isl_tiling_is_std_y(tiling
));
43 const uint32_t bs
= fmtl
->bs
;
44 const uint32_t is_Ys
= tiling
== ISL_TILING_Ys
;
48 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
49 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
51 *align_sa
= (struct isl_extent3d
) {
52 .w
= 1 << (12 - (ffs(bs
) - 1) + (4 * is_Ys
)),
58 /* See the Skylake BSpec > Memory Views > Common Surface Formats >
59 * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
62 *align_sa
= (struct isl_extent3d
) {
63 .w
= 1 << (6 - ((ffs(bs
) - 1) / 2) + (4 * is_Ys
)),
64 .h
= 1 << (6 - ((ffs(bs
) - 0) / 2) + (4 * is_Ys
)),
69 /* FINISHME(chadv): I don't trust this code. Untested. */
70 isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__
, __func__
);
72 switch (msaa_layout
) {
73 case ISL_MSAA_LAYOUT_NONE
:
74 case ISL_MSAA_LAYOUT_INTERLEAVED
:
76 case ISL_MSAA_LAYOUT_ARRAY
:
77 align_sa
->w
>>= (ffs(info
->samples
) - 0) / 2;
78 align_sa
->h
>>= (ffs(info
->samples
) - 1) / 2;
85 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
86 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
88 *align_sa
= (struct isl_extent3d
) {
89 .w
= 1 << (4 - ((ffs(bs
) + 1) / 3) + (4 * is_Ys
)),
90 .h
= 1 << (4 - ((ffs(bs
) - 1) / 3) + (2 * is_Ys
)),
91 .d
= 1 << (4 - ((ffs(bs
) - 0) / 3) + (2 * is_Ys
)),
96 unreachable("bad isl_surface_type");
100 gen9_choose_lod_alignment_el(const struct isl_device
*dev
,
101 const struct isl_surf_init_info
*restrict info
,
102 enum isl_tiling tiling
,
103 enum isl_msaa_layout msaa_layout
,
104 struct isl_extent3d
*lod_align_el
)
106 /* This BSpec text provides some insight into the hardware's alignment
107 * requirements [Skylake BSpec > Memory Views > Common Surface Formats >
108 * Surface Layout and Tiling > 2D Surfaces]:
110 * An LOD must be aligned to a cache-line except for some special cases
111 * related to Planar YUV surfaces. In general, the cache-alignment
112 * restriction implies there is a minimum height for an LOD of 4 texels.
113 * So, LODs which are smaller than 4 high are padded.
115 * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment:
117 * - For Sampling Engine and Render Target Surfaces: This field
118 * specifies the vertical alignment requirement in elements for the
119 * surface. [...] An element is defined as a pixel in uncompresed
120 * surface formats, and as a compression block in compressed surface
121 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
122 * element is a sample.
124 * - This field is used for 2D, CUBE, and 3D surface alignment when Tiled
125 * Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled).
126 * This field is ignored for 1D surfaces and also when Tiled Resource
127 * Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled).
129 * See the appropriate Alignment table in the "Surface Layout and
130 * Tiling" section under Common Surface Formats for the table of
131 * alignment values for Tiled Resrouces.
133 * - For uncompressed surfaces, the units of "j" are rows of pixels on
134 * the physical surface. For compressed texture formats, the units of
135 * "j" are in compression blocks, thus each increment in "j" is equal
136 * to h pixels, where h is the height of the compression block in
139 * - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16
141 * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal
144 * - For uncompressed surfaces, the units of "i" are pixels on the
145 * physical surface. For compressed texture formats, the units of "i"
146 * are in compression blocks, thus each increment in "i" is equal to
147 * w pixels, where w is the width of the compression block in pixels.
149 * - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16
152 if (isl_tiling_is_std_y(tiling
)) {
153 struct isl_extent3d lod_align_sa
;
154 gen9_calc_std_lod_alignment_sa(dev
, info
, tiling
, msaa_layout
,
157 *lod_align_el
= isl_extent3d_sa_to_el(info
->format
, lod_align_sa
);
161 if (info
->dim
== ISL_SURF_DIM_1D
) {
162 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
163 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
165 *lod_align_el
= isl_extent3d(64, 1, 1);
169 if (isl_format_is_compressed(info
->format
)) {
170 /* On Gen9, the meaning of RENDER_SURFACE_STATE's
171 * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for
172 * compressed formats. They now indicate a multiple of the compression
173 * block. For example, if the compression mode is ETC2 then HALIGN_4
174 * indicates a horizontal alignment of 16 pixels.
176 * To avoid wasting memory, choose the smallest alignment possible:
177 * HALIGN_4 and VALIGN_4.
179 *lod_align_el
= isl_extent3d(4, 4, 1);
183 gen8_choose_lod_alignment_el(dev
, info
, tiling
, msaa_layout
, lod_align_el
);