2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 VkResult
anv_CreateShader(
36 const VkShaderCreateInfo
* pCreateInfo
,
39 struct anv_device
*device
= (struct anv_device
*) _device
;
40 struct anv_shader
*shader
;
42 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_CREATE_INFO
);
44 shader
= anv_device_alloc(device
, sizeof(*shader
) + pCreateInfo
->codeSize
, 8,
45 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
47 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
49 shader
->size
= pCreateInfo
->codeSize
;
50 memcpy(shader
->data
, pCreateInfo
->pCode
, shader
->size
);
52 *pShader
= (VkShader
) shader
;
60 emit_vertex_input(struct anv_pipeline
*pipeline
, VkPipelineVertexInputCreateInfo
*info
)
62 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
64 bool instancing_enable
[32];
66 pipeline
->vb_used
= 0;
67 for (uint32_t i
= 0; i
< info
->bindingCount
; i
++) {
68 const VkVertexInputBindingDescription
*desc
=
69 &info
->pVertexBindingDescriptions
[i
];
71 pipeline
->vb_used
|= 1 << desc
->binding
;
72 pipeline
->binding_stride
[desc
->binding
] = desc
->strideInBytes
;
74 /* Step rate is programmed per vertex element (attribute), not
75 * binding. Set up a map of which bindings step per instance, for
76 * reference by vertex element setup. */
77 switch (desc
->stepRate
) {
79 case VK_VERTEX_INPUT_STEP_RATE_VERTEX
:
80 instancing_enable
[desc
->binding
] = false;
82 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE
:
83 instancing_enable
[desc
->binding
] = true;
88 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
89 GEN8_3DSTATE_VERTEX_ELEMENTS
);
91 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
92 const VkVertexInputAttributeDescription
*desc
=
93 &info
->pVertexAttributeDescriptions
[i
];
94 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
96 struct GEN8_VERTEX_ELEMENT_STATE element
= {
97 .VertexBufferIndex
= desc
->binding
,
99 .SourceElementFormat
= format
->surface_format
,
100 .EdgeFlagEnable
= false,
101 .SourceElementOffset
= desc
->offsetInBytes
,
102 .Component0Control
= VFCOMP_STORE_SRC
,
103 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
104 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
105 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
107 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
109 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
110 .InstancingEnable
= instancing_enable
[desc
->binding
],
111 .VertexElementIndex
= i
,
112 /* Vulkan so far doesn't have an instance divisor, so
113 * this is always 1 (ignored if not instancing). */
114 .InstanceDataStepRate
= 1);
117 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
118 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
119 .VertexIDComponentNumber
= 2,
120 .VertexIDElementOffset
= info
->bindingCount
,
121 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
122 .InstanceIDComponentNumber
= 3,
123 .InstanceIDElementOffset
= info
->bindingCount
);
127 emit_ia_state(struct anv_pipeline
*pipeline
,
128 VkPipelineIaStateCreateInfo
*info
,
129 const struct anv_pipeline_create_info
*extra
)
131 static const uint32_t vk_to_gen_primitive_type
[] = {
132 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
133 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
134 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
135 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
136 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
137 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
138 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ
] = _3DPRIM_LINELIST_ADJ
,
139 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ
] = _3DPRIM_LISTSTRIP_ADJ
,
140 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ
] = _3DPRIM_TRILIST_ADJ
,
141 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ
] = _3DPRIM_TRISTRIP_ADJ
,
142 [VK_PRIMITIVE_TOPOLOGY_PATCH
] = _3DPRIM_PATCHLIST_1
144 uint32_t topology
= vk_to_gen_primitive_type
[info
->topology
];
146 if (extra
&& extra
->use_rectlist
)
147 topology
= _3DPRIM_RECTLIST
;
149 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF
,
150 .IndexedDrawCutIndexEnable
= info
->primitiveRestartEnable
,
151 .CutIndex
= info
->primitiveRestartIndex
);
152 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
153 .PrimitiveTopologyType
= topology
);
157 emit_rs_state(struct anv_pipeline
*pipeline
, VkPipelineRsStateCreateInfo
*info
,
158 const struct anv_pipeline_create_info
*extra
)
160 static const uint32_t vk_to_gen_cullmode
[] = {
161 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
162 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
163 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
164 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
167 static const uint32_t vk_to_gen_fillmode
[] = {
168 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
169 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
170 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
173 static const uint32_t vk_to_gen_front_face
[] = {
174 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
175 [VK_FRONT_FACE_CW
] = Clockwise
178 static const uint32_t vk_to_gen_coordinate_origin
[] = {
179 [VK_COORDINATE_ORIGIN_UPPER_LEFT
] = UPPERLEFT
,
180 [VK_COORDINATE_ORIGIN_LOWER_LEFT
] = LOWERLEFT
183 struct GEN8_3DSTATE_SF sf
= {
184 GEN8_3DSTATE_SF_header
,
185 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
186 .TriangleStripListProvokingVertexSelect
=
187 info
->provokingVertex
== VK_PROVOKING_VERTEX_FIRST
? 0 : 2,
188 .LineStripListProvokingVertexSelect
=
189 info
->provokingVertex
== VK_PROVOKING_VERTEX_FIRST
? 0 : 1,
190 .TriangleFanProvokingVertexSelect
=
191 info
->provokingVertex
== VK_PROVOKING_VERTEX_FIRST
? 0 : 2,
192 .PointWidthSource
= info
->programPointSize
? Vertex
: State
,
195 /* FINISHME: bool32_t rasterizerDiscardEnable; */
197 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->state_sf
, &sf
);
199 struct GEN8_3DSTATE_RASTER raster
= {
200 GEN8_3DSTATE_RASTER_header
,
201 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
202 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
203 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
204 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
205 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
206 .ViewportZClipTestEnable
= info
->depthClipEnable
209 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->state_raster
, &raster
);
211 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
212 .ForceVertexURBEntryReadLength
= false,
213 .ForceVertexURBEntryReadOffset
= false,
214 .PointSpriteTextureCoordinateOrigin
=
215 vk_to_gen_coordinate_origin
[info
->pointOrigin
],
216 .NumberofSFOutputAttributes
=
217 pipeline
->wm_prog_data
.num_varying_inputs
);
222 emit_cb_state(struct anv_pipeline
*pipeline
, VkPipelineCbStateCreateInfo
*info
)
224 struct anv_device
*device
= pipeline
->device
;
226 static const uint32_t vk_to_gen_logic_op
[] = {
227 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
228 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
229 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
230 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
231 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
232 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
233 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
234 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
235 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
236 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
237 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
238 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
239 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
240 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
241 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
242 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
245 static const uint32_t vk_to_gen_blend
[] = {
246 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
247 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
248 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
249 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
250 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
251 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
252 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
253 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
254 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
255 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
256 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
257 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
258 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
259 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
260 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
261 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
262 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
263 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
264 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
267 static const uint32_t vk_to_gen_blend_op
[] = {
268 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
269 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
270 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
271 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
272 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
275 uint32_t num_dwords
= 1 + info
->attachmentCount
* 2;
276 pipeline
->blend_state
=
277 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
279 struct GEN8_BLEND_STATE blend_state
= {
280 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
283 uint32_t *state
= pipeline
->blend_state
.map
;
284 GEN8_BLEND_STATE_pack(NULL
, state
, &blend_state
);
286 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
287 const VkPipelineCbAttachmentState
*a
= &info
->pAttachments
[i
];
289 struct GEN8_BLEND_STATE_ENTRY entry
= {
290 .LogicOpEnable
= info
->logicOpEnable
,
291 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
292 .ColorBufferBlendEnable
= a
->blendEnable
,
293 .PreBlendSourceOnlyClampEnable
= false,
294 .PreBlendColorClampEnable
= false,
295 .PostBlendColorClampEnable
= false,
296 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
297 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
298 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
299 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
300 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
301 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
302 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
303 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
304 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
305 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
308 GEN8_BLEND_STATE_ENTRY_pack(NULL
, state
+ i
* 2 + 1, &entry
);
311 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
312 .BlendStatePointer
= pipeline
->blend_state
.offset
,
313 .BlendStatePointerValid
= true);
316 static const uint32_t vk_to_gen_compare_op
[] = {
317 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
318 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
319 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
320 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
321 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
322 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
323 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
324 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
327 static const uint32_t vk_to_gen_stencil_op
[] = {
328 [VK_STENCIL_OP_KEEP
] = 0,
329 [VK_STENCIL_OP_ZERO
] = 0,
330 [VK_STENCIL_OP_REPLACE
] = 0,
331 [VK_STENCIL_OP_INC_CLAMP
] = 0,
332 [VK_STENCIL_OP_DEC_CLAMP
] = 0,
333 [VK_STENCIL_OP_INVERT
] = 0,
334 [VK_STENCIL_OP_INC_WRAP
] = 0,
335 [VK_STENCIL_OP_DEC_WRAP
] = 0
339 emit_ds_state(struct anv_pipeline
*pipeline
, VkPipelineDsStateCreateInfo
*info
)
342 /* We're going to OR this together with the dynamic state. We need
343 * to make sure it's initialized to something useful.
345 memset(pipeline
->state_wm_depth_stencil
, 0,
346 sizeof(pipeline
->state_wm_depth_stencil
));
350 /* bool32_t depthBoundsEnable; // optional (depth_bounds_test) */
352 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
353 .DepthTestEnable
= info
->depthTestEnable
,
354 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
355 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
356 .DoubleSidedStencilEnable
= true,
358 .StencilTestEnable
= info
->stencilTestEnable
,
359 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
360 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
361 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
362 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
363 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
364 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
365 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
366 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
369 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->state_wm_depth_stencil
, &wm_depth_stencil
);
372 VkResult
anv_CreateGraphicsPipeline(
374 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
375 VkPipeline
* pPipeline
)
377 return anv_pipeline_create(device
, pCreateInfo
, NULL
, pPipeline
);
381 anv_pipeline_destroy(struct anv_device
*device
,
382 struct anv_object
*object
,
383 VkObjectType obj_type
)
385 struct anv_pipeline
*pipeline
= (struct anv_pipeline
*) object
;
387 assert(obj_type
== VK_OBJECT_TYPE_PIPELINE
);
389 anv_compiler_free(pipeline
);
390 anv_reloc_list_finish(&pipeline
->batch
.relocs
, pipeline
->device
);
391 anv_state_stream_finish(&pipeline
->program_stream
);
392 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
393 anv_device_free(pipeline
->device
, pipeline
);
399 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
400 const struct anv_pipeline_create_info
* extra
,
401 VkPipeline
* pPipeline
)
403 struct anv_device
*device
= (struct anv_device
*) _device
;
404 struct anv_pipeline
*pipeline
;
405 const struct anv_common
*common
;
406 VkPipelineShaderStageCreateInfo
*shader_create_info
;
407 VkPipelineIaStateCreateInfo
*ia_info
= NULL
;
408 VkPipelineRsStateCreateInfo
*rs_info
= NULL
;
409 VkPipelineDsStateCreateInfo
*ds_info
= NULL
;
410 VkPipelineCbStateCreateInfo
*cb_info
= NULL
;
411 VkPipelineVertexInputCreateInfo
*vi_info
= NULL
;
413 uint32_t offset
, length
;
415 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
417 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
418 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
419 if (pipeline
== NULL
)
420 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
422 pipeline
->base
.destructor
= anv_pipeline_destroy
;
423 pipeline
->device
= device
;
424 pipeline
->layout
= (struct anv_pipeline_layout
*) pCreateInfo
->layout
;
425 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
427 result
= anv_reloc_list_init(&pipeline
->batch
.relocs
, device
);
428 if (result
!= VK_SUCCESS
) {
429 anv_device_free(device
, pipeline
);
432 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
433 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
435 anv_state_stream_init(&pipeline
->program_stream
,
436 &device
->instruction_block_pool
);
438 for (common
= pCreateInfo
->pNext
; common
; common
= common
->pNext
) {
439 switch (common
->sType
) {
440 case VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_CREATE_INFO
:
441 vi_info
= (VkPipelineVertexInputCreateInfo
*) common
;
443 case VK_STRUCTURE_TYPE_PIPELINE_IA_STATE_CREATE_INFO
:
444 ia_info
= (VkPipelineIaStateCreateInfo
*) common
;
446 case VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO
:
447 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO");
449 case VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO
:
450 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO");
452 case VK_STRUCTURE_TYPE_PIPELINE_RS_STATE_CREATE_INFO
:
453 rs_info
= (VkPipelineRsStateCreateInfo
*) common
;
455 case VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO
:
456 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO");
458 case VK_STRUCTURE_TYPE_PIPELINE_CB_STATE_CREATE_INFO
:
459 cb_info
= (VkPipelineCbStateCreateInfo
*) common
;
461 case VK_STRUCTURE_TYPE_PIPELINE_DS_STATE_CREATE_INFO
:
462 ds_info
= (VkPipelineDsStateCreateInfo
*) common
;
464 case VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
:
465 shader_create_info
= (VkPipelineShaderStageCreateInfo
*) common
;
466 pipeline
->shaders
[shader_create_info
->shader
.stage
] =
467 (struct anv_shader
*) shader_create_info
->shader
.shader
;
474 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
476 anv_compiler_run(device
->compiler
, pipeline
);
478 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
479 * hard code this to num_attributes - 2. This is because the attributes
480 * include VUE header and position, which aren't counted as varying
482 if (pipeline
->vs_simd8
== NO_KERNEL
)
483 pipeline
->wm_prog_data
.num_varying_inputs
= vi_info
->attributeCount
- 2;
486 emit_vertex_input(pipeline
, vi_info
);
488 emit_ia_state(pipeline
, ia_info
, extra
);
490 emit_rs_state(pipeline
, rs_info
, extra
);
491 emit_ds_state(pipeline
, ds_info
);
492 emit_cb_state(pipeline
, cb_info
);
494 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_STATISTICS
,
495 .StatisticsEnable
= true);
496 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_HS
, .Enable
= false);
497 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_TE
, .TEEnable
= false);
498 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_DS
, .FunctionEnable
= false);
499 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
501 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
502 .ConstantBufferOffset
= 0,
503 .ConstantBufferSize
= 4);
504 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
505 .ConstantBufferOffset
= 4,
506 .ConstantBufferSize
= 4);
507 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
508 .ConstantBufferOffset
= 8,
509 .ConstantBufferSize
= 4);
511 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM_CHROMAKEY
,
512 .ChromaKeyKillEnable
= false);
513 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE_SWIZ
);
514 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_AA_LINE_PARAMETERS
);
516 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
518 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
519 .MinimumPointWidth
= 0.125,
520 .MaximumPointWidth
= 255.875);
522 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
523 .StatisticsEnable
= true,
524 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
525 .LineAntialiasingRegionWidth
= _10pixels
,
526 .EarlyDepthStencilControl
= NORMAL
,
527 .ForceThreadDispatchEnable
= NORMAL
,
528 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
529 .BarycentricInterpolationMode
=
530 pipeline
->wm_prog_data
.barycentric_interp_modes
);
532 uint32_t samples
= 1;
533 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
534 bool enable_sampling
= samples
> 1 ? true : false;
536 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
537 .PixelPositionOffsetEnable
= enable_sampling
,
538 .PixelLocation
= CENTER
,
539 .NumberofMultisamples
= log2_samples
);
541 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
542 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
543 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
544 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
546 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
547 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
548 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
549 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
551 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
552 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
553 .HSURBEntryAllocationSize
= 0,
554 .HSNumberofURBEntries
= 0);
556 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
557 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
558 .DSURBEntryAllocationSize
= 0,
559 .DSNumberofURBEntries
= 0);
561 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
563 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
565 if (pipeline
->gs_vec4
== NO_KERNEL
)
566 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
568 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
569 .SingleProgramFlow
= false,
570 .KernelStartPointer
= pipeline
->gs_vec4
,
571 .VectorMaskEnable
= Vmask
,
573 .BindingTableEntryCount
= 0,
574 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
576 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
577 .PerThreadScratchSpace
= ffs(gs_prog_data
->base
.base
.total_scratch
/ 2048),
579 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
580 .OutputTopology
= gs_prog_data
->output_topology
,
581 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
582 .DispatchGRFStartRegisterForURBData
=
583 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
585 .MaximumNumberofThreads
= device
->info
.max_gs_threads
,
586 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
587 //pipeline->gs_prog_data.dispatch_mode |
588 .StatisticsEnable
= true,
589 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
590 .ReorderMode
= TRAILING
,
593 .ControlDataFormat
= gs_prog_data
->control_data_format
,
595 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
596 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
597 * UserClipDistanceCullTestEnableBitmask(v)
600 .VertexURBEntryOutputReadOffset
= offset
,
601 .VertexURBEntryOutputLength
= length
);
603 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
604 /* Skip the VUE header and position slots */
606 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
608 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
609 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
610 .FunctionEnable
= false,
611 .VertexURBEntryOutputReadOffset
= 1,
612 /* Even if VS is disabled, SBE still gets the amount of
613 * vertex data to read from this field. We use attribute
614 * count - 1, as we don't count the VUE header here. */
615 .VertexURBEntryOutputLength
=
616 DIV_ROUND_UP(vi_info
->attributeCount
- 1, 2));
618 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
619 .KernelStartPointer
= pipeline
->vs_simd8
,
620 .SingleVertexDispatch
= Multiple
,
621 .VectorMaskEnable
= Dmask
,
623 .BindingTableEntryCount
=
624 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
625 .ThreadDispatchPriority
= Normal
,
626 .FloatingPointMode
= IEEE754
,
627 .IllegalOpcodeExceptionEnable
= false,
628 .AccessesUAV
= false,
629 .SoftwareExceptionEnable
= false,
631 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
632 .PerThreadScratchSpace
= ffs(vue_prog_data
->base
.total_scratch
/ 2048),
634 .DispatchGRFStartRegisterForURBData
=
635 vue_prog_data
->base
.dispatch_grf_start_reg
,
636 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
637 .VertexURBEntryReadOffset
= 0,
639 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
640 .StatisticsEnable
= false,
641 .SIMD8DispatchEnable
= true,
642 .VertexCacheDisable
= ia_info
->disableVertexReuse
,
643 .FunctionEnable
= true,
645 .VertexURBEntryOutputReadOffset
= offset
,
646 .VertexURBEntryOutputLength
= length
,
647 .UserClipDistanceClipTestEnableBitmask
= 0,
648 .UserClipDistanceCullTestEnableBitmask
= 0);
650 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
651 uint32_t ksp0
, ksp2
, grf_start0
, grf_start2
;
655 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
656 ksp0
= pipeline
->ps_simd8
;
657 grf_start0
= wm_prog_data
->base
.dispatch_grf_start_reg
;
658 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
659 ksp2
= pipeline
->ps_simd16
;
660 grf_start2
= wm_prog_data
->dispatch_grf_start_reg_16
;
662 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
663 ksp0
= pipeline
->ps_simd16
;
664 grf_start0
= wm_prog_data
->dispatch_grf_start_reg_16
;
666 unreachable("no ps shader");
669 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
670 .KernelStartPointer0
= ksp0
,
672 .SingleProgramFlow
= false,
673 .VectorMaskEnable
= true,
676 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
677 .PerThreadScratchSpace
= ffs(wm_prog_data
->base
.total_scratch
/ 2048),
679 .MaximumNumberofThreadsPerPSD
= 64 - 2,
680 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
681 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
682 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
683 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
684 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
685 ._32PixelDispatchEnable
= false,
687 .DispatchGRFStartRegisterForConstantSetupData0
= grf_start0
,
688 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
689 .DispatchGRFStartRegisterForConstantSetupData2
= grf_start2
,
691 .KernelStartPointer1
= 0,
692 .KernelStartPointer2
= ksp2
);
694 bool per_sample_ps
= false;
695 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
696 .PixelShaderValid
= true,
697 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
698 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
699 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
700 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
701 .PixelShaderIsPerSample
= per_sample_ps
);
703 *pPipeline
= (VkPipeline
) pipeline
;
708 VkResult
anv_CreateGraphicsPipelineDerivative(
710 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
711 VkPipeline basePipeline
,
712 VkPipeline
* pPipeline
)
714 stub_return(VK_UNSUPPORTED
);
717 VkResult
anv_CreateComputePipeline(
719 const VkComputePipelineCreateInfo
* pCreateInfo
,
720 VkPipeline
* pPipeline
)
722 struct anv_device
*device
= (struct anv_device
*) _device
;
723 struct anv_pipeline
*pipeline
;
726 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
728 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
729 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
730 if (pipeline
== NULL
)
731 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
733 pipeline
->base
.destructor
= anv_pipeline_destroy
;
734 pipeline
->device
= device
;
735 pipeline
->layout
= (struct anv_pipeline_layout
*) pCreateInfo
->layout
;
737 result
= anv_reloc_list_init(&pipeline
->batch
.relocs
, device
);
738 if (result
!= VK_SUCCESS
) {
739 anv_device_free(device
, pipeline
);
742 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
743 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
745 anv_state_stream_init(&pipeline
->program_stream
,
746 &device
->instruction_block_pool
);
748 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
750 pipeline
->shaders
[VK_SHADER_STAGE_COMPUTE
] =
751 (struct anv_shader
*) pCreateInfo
->cs
.shader
;
753 pipeline
->use_repclear
= false;
755 anv_compiler_run(device
->compiler
, pipeline
);
757 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
759 anv_batch_emit(&pipeline
->batch
, GEN8_MEDIA_VFE_STATE
,
760 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
761 .PerThreadScratchSpace
= ffs(cs_prog_data
->base
.total_scratch
/ 2048),
762 .ScratchSpaceBasePointerHigh
= 0,
765 .MaximumNumberofThreads
= device
->info
.max_cs_threads
- 1,
766 .NumberofURBEntries
= 2,
767 .ResetGatewayTimer
= true,
768 .BypassGatewayControl
= true,
769 .URBEntryAllocationSize
= 2,
770 .CURBEAllocationSize
= 0);
772 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
773 uint32_t group_size
= prog_data
->local_size
[0] *
774 prog_data
->local_size
[1] * prog_data
->local_size
[2];
775 pipeline
->cs_thread_width_max
= DIV_ROUND_UP(group_size
, prog_data
->simd_size
);
776 uint32_t remainder
= group_size
& (prog_data
->simd_size
- 1);
779 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
781 pipeline
->cs_right_mask
= ~0u >> (32 - prog_data
->simd_size
);
784 *pPipeline
= (VkPipeline
) pipeline
;
789 VkResult
anv_StorePipeline(
795 stub_return(VK_UNSUPPORTED
);
798 VkResult
anv_LoadPipeline(
802 VkPipeline
* pPipeline
)
804 stub_return(VK_UNSUPPORTED
);
807 VkResult
anv_LoadPipelineDerivative(
811 VkPipeline basePipeline
,
812 VkPipeline
* pPipeline
)
814 stub_return(VK_UNSUPPORTED
);
817 // Pipeline layout functions
819 VkResult
anv_CreatePipelineLayout(
821 const VkPipelineLayoutCreateInfo
* pCreateInfo
,
822 VkPipelineLayout
* pPipelineLayout
)
824 struct anv_device
*device
= (struct anv_device
*) _device
;
825 struct anv_pipeline_layout
*layout
;
827 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
);
829 layout
= anv_device_alloc(device
, sizeof(*layout
), 8,
830 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
832 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
834 layout
->num_sets
= pCreateInfo
->descriptorSetCount
;
836 uint32_t surface_start
[VK_SHADER_STAGE_NUM
] = { 0, };
837 uint32_t sampler_start
[VK_SHADER_STAGE_NUM
] = { 0, };
839 for (uint32_t s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++) {
840 layout
->stage
[s
].surface_count
= 0;
841 layout
->stage
[s
].sampler_count
= 0;
844 for (uint32_t i
= 0; i
< pCreateInfo
->descriptorSetCount
; i
++) {
845 struct anv_descriptor_set_layout
*set_layout
=
846 (struct anv_descriptor_set_layout
*) pCreateInfo
->pSetLayouts
[i
];
848 layout
->set
[i
].layout
= set_layout
;
849 for (uint32_t s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++) {
850 layout
->set
[i
].surface_start
[s
] = surface_start
[s
];
851 surface_start
[s
] += set_layout
->stage
[s
].surface_count
;
852 layout
->set
[i
].sampler_start
[s
] = sampler_start
[s
];
853 sampler_start
[s
] += set_layout
->stage
[s
].sampler_count
;
855 layout
->stage
[s
].surface_count
+= set_layout
->stage
[s
].surface_count
;
856 layout
->stage
[s
].sampler_count
+= set_layout
->stage
[s
].sampler_count
;
860 *pPipelineLayout
= (VkPipelineLayout
) layout
;