vk: Program depth bias
[mesa.git] / src / vulkan / pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "private.h"
31
32 // Shader functions
33
34 VkResult anv_CreateShader(
35 VkDevice _device,
36 const VkShaderCreateInfo* pCreateInfo,
37 VkShader* pShader)
38 {
39 struct anv_device *device = (struct anv_device *) _device;
40 struct anv_shader *shader;
41
42 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_CREATE_INFO);
43
44 shader = anv_device_alloc(device, sizeof(*shader) + pCreateInfo->codeSize, 8,
45 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
46 if (shader == NULL)
47 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
48
49 shader->size = pCreateInfo->codeSize;
50 memcpy(shader->data, pCreateInfo->pCode, shader->size);
51
52 *pShader = (VkShader) shader;
53
54 return VK_SUCCESS;
55 }
56
57 // Pipeline functions
58
59 static void
60 emit_vertex_input(struct anv_pipeline *pipeline, VkPipelineVertexInputCreateInfo *info)
61 {
62 const uint32_t num_dwords = 1 + info->attributeCount * 2;
63 uint32_t *p;
64 bool instancing_enable[32];
65
66 pipeline->vb_used = 0;
67 for (uint32_t i = 0; i < info->bindingCount; i++) {
68 const VkVertexInputBindingDescription *desc =
69 &info->pVertexBindingDescriptions[i];
70
71 pipeline->vb_used |= 1 << desc->binding;
72 pipeline->binding_stride[desc->binding] = desc->strideInBytes;
73
74 /* Step rate is programmed per vertex element (attribute), not
75 * binding. Set up a map of which bindings step per instance, for
76 * reference by vertex element setup. */
77 switch (desc->stepRate) {
78 default:
79 case VK_VERTEX_INPUT_STEP_RATE_VERTEX:
80 instancing_enable[desc->binding] = false;
81 break;
82 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE:
83 instancing_enable[desc->binding] = true;
84 break;
85 }
86 }
87
88 p = anv_batch_emitn(&pipeline->batch, num_dwords,
89 GEN8_3DSTATE_VERTEX_ELEMENTS);
90
91 for (uint32_t i = 0; i < info->attributeCount; i++) {
92 const VkVertexInputAttributeDescription *desc =
93 &info->pVertexAttributeDescriptions[i];
94 const struct anv_format *format = anv_format_for_vk_format(desc->format);
95
96 struct GEN8_VERTEX_ELEMENT_STATE element = {
97 .VertexBufferIndex = desc->binding,
98 .Valid = true,
99 .SourceElementFormat = format->format,
100 .EdgeFlagEnable = false,
101 .SourceElementOffset = desc->offsetInBytes,
102 .Component0Control = VFCOMP_STORE_SRC,
103 .Component1Control = format->channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
104 .Component2Control = format->channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
105 .Component3Control = format->channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
106 };
107 GEN8_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
108
109 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_INSTANCING,
110 .InstancingEnable = instancing_enable[desc->binding],
111 .VertexElementIndex = i,
112 /* Vulkan so far doesn't have an instance divisor, so
113 * this is always 1 (ignored if not instancing). */
114 .InstanceDataStepRate = 1);
115 }
116
117 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_SGVS,
118 .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
119 .VertexIDComponentNumber = 2,
120 .VertexIDElementOffset = info->bindingCount,
121 .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
122 .InstanceIDComponentNumber = 3,
123 .InstanceIDElementOffset = info->bindingCount);
124 }
125
126 static void
127 emit_ia_state(struct anv_pipeline *pipeline,
128 VkPipelineIaStateCreateInfo *info,
129 const struct anv_pipeline_create_info *extra)
130 {
131 static const uint32_t vk_to_gen_primitive_type[] = {
132 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
133 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
134 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
135 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
136 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
137 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
138 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ] = _3DPRIM_LINELIST_ADJ,
139 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ] = _3DPRIM_LISTSTRIP_ADJ,
140 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ] = _3DPRIM_TRILIST_ADJ,
141 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ] = _3DPRIM_TRISTRIP_ADJ,
142 [VK_PRIMITIVE_TOPOLOGY_PATCH] = _3DPRIM_PATCHLIST_1
143 };
144 uint32_t topology = vk_to_gen_primitive_type[info->topology];
145
146 if (extra && extra->use_rectlist)
147 topology = _3DPRIM_RECTLIST;
148
149 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF,
150 .IndexedDrawCutIndexEnable = info->primitiveRestartEnable,
151 .CutIndex = info->primitiveRestartIndex);
152 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_TOPOLOGY,
153 .PrimitiveTopologyType = topology);
154 }
155
156 static void
157 emit_rs_state(struct anv_pipeline *pipeline, VkPipelineRsStateCreateInfo *info,
158 const struct anv_pipeline_create_info *extra)
159 {
160 static const uint32_t vk_to_gen_cullmode[] = {
161 [VK_CULL_MODE_NONE] = CULLMODE_NONE,
162 [VK_CULL_MODE_FRONT] = CULLMODE_FRONT,
163 [VK_CULL_MODE_BACK] = CULLMODE_BACK,
164 [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
165 };
166
167 static const uint32_t vk_to_gen_fillmode[] = {
168 [VK_FILL_MODE_POINTS] = RASTER_POINT,
169 [VK_FILL_MODE_WIREFRAME] = RASTER_WIREFRAME,
170 [VK_FILL_MODE_SOLID] = RASTER_SOLID
171 };
172
173 static const uint32_t vk_to_gen_front_face[] = {
174 [VK_FRONT_FACE_CCW] = CounterClockwise,
175 [VK_FRONT_FACE_CW] = Clockwise
176 };
177
178 static const uint32_t vk_to_gen_coordinate_origin[] = {
179 [VK_COORDINATE_ORIGIN_UPPER_LEFT] = UPPERLEFT,
180 [VK_COORDINATE_ORIGIN_LOWER_LEFT] = LOWERLEFT
181 };
182
183 struct GEN8_3DSTATE_SF sf = {
184 GEN8_3DSTATE_SF_header,
185 .ViewportTransformEnable = !(extra && extra->disable_viewport),
186 .TriangleStripListProvokingVertexSelect =
187 info->provokingVertex == VK_PROVOKING_VERTEX_FIRST ? 0 : 2,
188 .LineStripListProvokingVertexSelect =
189 info->provokingVertex == VK_PROVOKING_VERTEX_FIRST ? 0 : 1,
190 .TriangleFanProvokingVertexSelect =
191 info->provokingVertex == VK_PROVOKING_VERTEX_FIRST ? 0 : 2,
192 .PointWidthSource = info->programPointSize ? Vertex : State,
193 };
194
195 /* bool32_t rasterizerDiscardEnable; */
196
197
198 GEN8_3DSTATE_SF_pack(NULL, pipeline->state_sf, &sf);
199
200 struct GEN8_3DSTATE_RASTER raster = {
201 .FrontWinding = vk_to_gen_front_face[info->frontFace],
202 .CullMode = vk_to_gen_cullmode[info->cullMode],
203 .FrontFaceFillMode = vk_to_gen_fillmode[info->fillMode],
204 .BackFaceFillMode = vk_to_gen_fillmode[info->fillMode],
205 .ScissorRectangleEnable = !(extra && extra->disable_scissor),
206 .ViewportZClipTestEnable = info->depthClipEnable
207 };
208
209 GEN8_3DSTATE_RASTER_pack(NULL, pipeline->state_raster, &raster);
210
211 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_SBE,
212 .ForceVertexURBEntryReadLength = false,
213 .ForceVertexURBEntryReadOffset = false,
214 .PointSpriteTextureCoordinateOrigin =
215 vk_to_gen_coordinate_origin[info->pointOrigin],
216 .NumberofSFOutputAttributes =
217 pipeline->wm_prog_data.num_varying_inputs);
218
219 }
220
221 static const uint32_t vk_to_gen_compare_op[] = {
222 [VK_COMPARE_OP_NEVER] = COMPAREFUNCTION_NEVER,
223 [VK_COMPARE_OP_LESS] = COMPAREFUNCTION_LESS,
224 [VK_COMPARE_OP_EQUAL] = COMPAREFUNCTION_EQUAL,
225 [VK_COMPARE_OP_LESS_EQUAL] = COMPAREFUNCTION_LEQUAL,
226 [VK_COMPARE_OP_GREATER] = COMPAREFUNCTION_GREATER,
227 [VK_COMPARE_OP_NOT_EQUAL] = COMPAREFUNCTION_NOTEQUAL,
228 [VK_COMPARE_OP_GREATER_EQUAL] = COMPAREFUNCTION_GEQUAL,
229 [VK_COMPARE_OP_ALWAYS] = COMPAREFUNCTION_ALWAYS,
230 };
231
232 static const uint32_t vk_to_gen_stencil_op[] = {
233 [VK_STENCIL_OP_KEEP] = 0,
234 [VK_STENCIL_OP_ZERO] = 0,
235 [VK_STENCIL_OP_REPLACE] = 0,
236 [VK_STENCIL_OP_INC_CLAMP] = 0,
237 [VK_STENCIL_OP_DEC_CLAMP] = 0,
238 [VK_STENCIL_OP_INVERT] = 0,
239 [VK_STENCIL_OP_INC_WRAP] = 0,
240 [VK_STENCIL_OP_DEC_WRAP] = 0
241 };
242
243 static void
244 emit_ds_state(struct anv_pipeline *pipeline, VkPipelineDsStateCreateInfo *info)
245 {
246 /* bool32_t depthBoundsEnable; // optional (depth_bounds_test) */
247
248 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
249 .DepthTestEnable = info->depthTestEnable,
250 .DepthBufferWriteEnable = info->depthWriteEnable,
251 .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
252 .DoubleSidedStencilEnable = true,
253
254 .StencilTestEnable = info->stencilTestEnable,
255 .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
256 .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
257 .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
258 .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
259 .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
260 .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
261 .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
262 .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
263 };
264
265 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, pipeline->state_wm_depth_stencil, &wm_depth_stencil);
266 }
267
268 VkResult anv_CreateGraphicsPipeline(
269 VkDevice device,
270 const VkGraphicsPipelineCreateInfo* pCreateInfo,
271 VkPipeline* pPipeline)
272 {
273 return anv_pipeline_create(device, pCreateInfo, NULL, pPipeline);
274 }
275
276 static void
277 anv_pipeline_destroy(struct anv_device *device,
278 struct anv_object *object,
279 VkObjectType obj_type)
280 {
281 struct anv_pipeline *pipeline = (struct anv_pipeline*) object;
282
283 assert(obj_type == VK_OBJECT_TYPE_PIPELINE);
284
285 anv_compiler_free(pipeline);
286 anv_batch_finish(&pipeline->batch, pipeline->device);
287 anv_device_free(pipeline->device, pipeline);
288 }
289
290 VkResult
291 anv_pipeline_create(
292 VkDevice _device,
293 const VkGraphicsPipelineCreateInfo* pCreateInfo,
294 const struct anv_pipeline_create_info * extra,
295 VkPipeline* pPipeline)
296 {
297 struct anv_device *device = (struct anv_device *) _device;
298 struct anv_pipeline *pipeline;
299 const struct anv_common *common;
300 VkPipelineShaderStageCreateInfo *shader_create_info;
301 VkPipelineIaStateCreateInfo *ia_info = NULL;
302 VkPipelineRsStateCreateInfo *rs_info = NULL;
303 VkPipelineDsStateCreateInfo *ds_info = NULL;
304 VkPipelineVertexInputCreateInfo *vi_info;
305 VkResult result;
306 uint32_t offset, length;
307
308 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
309
310 pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
311 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
312 if (pipeline == NULL)
313 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
314
315 pipeline->base.destructor = anv_pipeline_destroy;
316 pipeline->device = device;
317 pipeline->layout = (struct anv_pipeline_layout *) pCreateInfo->layout;
318 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
319 result = anv_batch_init(&pipeline->batch, device);
320 if (result != VK_SUCCESS)
321 goto fail;
322
323 anv_state_stream_init(&pipeline->program_stream,
324 &device->instruction_block_pool);
325
326 for (common = pCreateInfo->pNext; common; common = common->pNext) {
327 switch (common->sType) {
328 case VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_CREATE_INFO:
329 vi_info = (VkPipelineVertexInputCreateInfo *) common;
330 break;
331 case VK_STRUCTURE_TYPE_PIPELINE_IA_STATE_CREATE_INFO:
332 ia_info = (VkPipelineIaStateCreateInfo *) common;
333 break;
334 case VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO:
335 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO");
336 break;
337 case VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO:
338 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO");
339 break;
340 case VK_STRUCTURE_TYPE_PIPELINE_RS_STATE_CREATE_INFO:
341 rs_info = (VkPipelineRsStateCreateInfo *) common;
342 break;
343 case VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO:
344 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO");
345 break;
346 case VK_STRUCTURE_TYPE_PIPELINE_CB_STATE_CREATE_INFO:
347 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_CB_STATE_CREATE_INFO");
348 break;
349 case VK_STRUCTURE_TYPE_PIPELINE_DS_STATE_CREATE_INFO:
350 ds_info = (VkPipelineDsStateCreateInfo *) common;
351 break;
352 case VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO:
353 shader_create_info = (VkPipelineShaderStageCreateInfo *) common;
354 pipeline->shaders[shader_create_info->shader.stage] =
355 (struct anv_shader *) shader_create_info->shader.shader;
356 break;
357 default:
358 break;
359 }
360 }
361
362 pipeline->use_repclear = extra && extra->use_repclear;
363
364 anv_compiler_run(device->compiler, pipeline);
365
366 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
367 * hard code this to num_attributes - 2. This is because the attributes
368 * include VUE header and position, which aren't counted as varying
369 * inputs. */
370 if (pipeline->vs_simd8 == NO_KERNEL)
371 pipeline->wm_prog_data.num_varying_inputs = vi_info->attributeCount - 2;
372
373 assert(vi_info);
374 emit_vertex_input(pipeline, vi_info);
375 assert(ia_info);
376 emit_ia_state(pipeline, ia_info, extra);
377 assert(rs_info);
378 emit_rs_state(pipeline, rs_info, extra);
379 /* ds_info is optional if we're not using depth or stencil buffers, ps is
380 * optional for depth-only rendering. */
381 if (ds_info)
382 emit_ds_state(pipeline, ds_info);
383
384 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_CLIP,
385 .ClipEnable = true,
386 .ViewportXYClipTestEnable = !(extra && extra->disable_viewport));
387
388 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_WM,
389 .StatisticsEnable = true,
390 .LineEndCapAntialiasingRegionWidth = _05pixels,
391 .LineAntialiasingRegionWidth = _10pixels,
392 .EarlyDepthStencilControl = NORMAL,
393 .ForceThreadDispatchEnable = NORMAL,
394 .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
395 .BarycentricInterpolationMode =
396 pipeline->wm_prog_data.barycentric_interp_modes);
397
398 uint32_t samples = 1;
399 uint32_t log2_samples = __builtin_ffs(samples) - 1;
400 bool enable_sampling = samples > 1 ? true : false;
401
402 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_MULTISAMPLE,
403 .PixelPositionOffsetEnable = enable_sampling,
404 .PixelLocation = CENTER,
405 .NumberofMultisamples = log2_samples);
406
407 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_VS,
408 .VSURBStartingAddress = pipeline->urb.vs_start,
409 .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
410 .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
411
412 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_GS,
413 .GSURBStartingAddress = pipeline->urb.gs_start,
414 .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
415 .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
416
417 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_HS,
418 .HSURBStartingAddress = pipeline->urb.vs_start,
419 .HSURBEntryAllocationSize = 0,
420 .HSNumberofURBEntries = 0);
421
422 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_DS,
423 .DSURBStartingAddress = pipeline->urb.vs_start,
424 .DSURBEntryAllocationSize = 0,
425 .DSNumberofURBEntries = 0);
426
427 const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
428 offset = 1;
429 length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
430
431 if (pipeline->gs_vec4 == NO_KERNEL)
432 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_GS, .Enable = false);
433 else
434 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_GS,
435 .SingleProgramFlow = false,
436 .KernelStartPointer = pipeline->gs_vec4,
437 .VectorMaskEnable = Vmask,
438 .SamplerCount = 0,
439 .BindingTableEntryCount = 0,
440 .ExpectedVertexCount = pipeline->gs_vertex_count,
441
442 .PerThreadScratchSpace = 0,
443 .ScratchSpaceBasePointer = 0,
444
445 .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
446 .OutputTopology = gs_prog_data->output_topology,
447 .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
448 .DispatchGRFStartRegisterForURBData =
449 gs_prog_data->base.base.dispatch_grf_start_reg,
450
451 .MaximumNumberofThreads = device->info.max_gs_threads,
452 .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
453 //pipeline->gs_prog_data.dispatch_mode |
454 .StatisticsEnable = true,
455 .IncludePrimitiveID = gs_prog_data->include_primitive_id,
456 .ReorderMode = TRAILING,
457 .Enable = true,
458
459 .ControlDataFormat = gs_prog_data->control_data_format,
460
461 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
462 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
463 * UserClipDistanceCullTestEnableBitmask(v)
464 */
465
466 .VertexURBEntryOutputReadOffset = offset,
467 .VertexURBEntryOutputLength = length);
468
469 //trp_generate_blend_hw_cmds(batch, pipeline);
470
471 const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
472 /* Skip the VUE header and position slots */
473 offset = 1;
474 length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
475
476 if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
477 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VS,
478 .FunctionEnable = false,
479 .VertexURBEntryOutputReadOffset = 1,
480 /* Even if VS is disabled, SBE still gets the amount of
481 * vertex data to read from this field. We use attribute
482 * count - 1, as we don't count the VUE header here. */
483 .VertexURBEntryOutputLength =
484 DIV_ROUND_UP(vi_info->attributeCount - 1, 2));
485 else
486 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VS,
487 .KernelStartPointer = pipeline->vs_simd8,
488 .SingleVertexDispatch = Multiple,
489 .VectorMaskEnable = Dmask,
490 .SamplerCount = 0,
491 .BindingTableEntryCount =
492 vue_prog_data->base.binding_table.size_bytes / 4,
493 .ThreadDispatchPriority = Normal,
494 .FloatingPointMode = IEEE754,
495 .IllegalOpcodeExceptionEnable = false,
496 .AccessesUAV = false,
497 .SoftwareExceptionEnable = false,
498
499 /* FIXME: pointer needs to be assigned outside as it aliases
500 * PerThreadScratchSpace.
501 */
502 .ScratchSpaceBasePointer = 0,
503 .PerThreadScratchSpace = 0,
504
505 .DispatchGRFStartRegisterForURBData =
506 vue_prog_data->base.dispatch_grf_start_reg,
507 .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
508 .VertexURBEntryReadOffset = 0,
509
510 .MaximumNumberofThreads = device->info.max_vs_threads - 1,
511 .StatisticsEnable = false,
512 .SIMD8DispatchEnable = true,
513 .VertexCacheDisable = ia_info->disableVertexReuse,
514 .FunctionEnable = true,
515
516 .VertexURBEntryOutputReadOffset = offset,
517 .VertexURBEntryOutputLength = length,
518 .UserClipDistanceClipTestEnableBitmask = 0,
519 .UserClipDistanceCullTestEnableBitmask = 0);
520
521 const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
522 uint32_t ksp0, ksp2, grf_start0, grf_start2;
523
524 ksp2 = 0;
525 grf_start2 = 0;
526 if (pipeline->ps_simd8 != NO_KERNEL) {
527 ksp0 = pipeline->ps_simd8;
528 grf_start0 = wm_prog_data->base.dispatch_grf_start_reg;
529 if (pipeline->ps_simd16 != NO_KERNEL) {
530 ksp2 = pipeline->ps_simd16;
531 grf_start2 = wm_prog_data->dispatch_grf_start_reg_16;
532 }
533 } else if (pipeline->ps_simd16 != NO_KERNEL) {
534 ksp0 = pipeline->ps_simd16;
535 grf_start0 = wm_prog_data->dispatch_grf_start_reg_16;
536 } else {
537 unreachable("no ps shader");
538 }
539
540 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PS,
541 .KernelStartPointer0 = ksp0,
542
543 .SingleProgramFlow = false,
544 .VectorMaskEnable = true,
545 .SamplerCount = 1,
546
547 .ScratchSpaceBasePointer = 0,
548 .PerThreadScratchSpace = 0,
549
550 .MaximumNumberofThreadsPerPSD = 64 - 2,
551 .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
552 POSOFFSET_SAMPLE: POSOFFSET_NONE,
553 .PushConstantEnable = wm_prog_data->base.nr_params > 0,
554 ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
555 ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
556 ._32PixelDispatchEnable = false,
557
558 .DispatchGRFStartRegisterForConstantSetupData0 = grf_start0,
559 .DispatchGRFStartRegisterForConstantSetupData1 = 0,
560 .DispatchGRFStartRegisterForConstantSetupData2 = grf_start2,
561
562 .KernelStartPointer1 = 0,
563 .KernelStartPointer2 = ksp2);
564
565 bool per_sample_ps = false;
566 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PS_EXTRA,
567 .PixelShaderValid = true,
568 .PixelShaderKillsPixel = wm_prog_data->uses_kill,
569 .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
570 .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
571 .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
572 .PixelShaderIsPerSample = per_sample_ps);
573
574 *pPipeline = (VkPipeline) pipeline;
575
576 return VK_SUCCESS;
577
578 fail:
579 anv_device_free(device, pipeline);
580
581 return result;
582 }
583
584 VkResult anv_CreateGraphicsPipelineDerivative(
585 VkDevice device,
586 const VkGraphicsPipelineCreateInfo* pCreateInfo,
587 VkPipeline basePipeline,
588 VkPipeline* pPipeline)
589 {
590 stub_return(VK_UNSUPPORTED);
591 }
592
593 VkResult anv_CreateComputePipeline(
594 VkDevice device,
595 const VkComputePipelineCreateInfo* pCreateInfo,
596 VkPipeline* pPipeline)
597 {
598 stub_return(VK_UNSUPPORTED);
599 }
600
601 VkResult anv_StorePipeline(
602 VkDevice device,
603 VkPipeline pipeline,
604 size_t* pDataSize,
605 void* pData)
606 {
607 stub_return(VK_UNSUPPORTED);
608 }
609
610 VkResult anv_LoadPipeline(
611 VkDevice device,
612 size_t dataSize,
613 const void* pData,
614 VkPipeline* pPipeline)
615 {
616 stub_return(VK_UNSUPPORTED);
617 }
618
619 VkResult anv_LoadPipelineDerivative(
620 VkDevice device,
621 size_t dataSize,
622 const void* pData,
623 VkPipeline basePipeline,
624 VkPipeline* pPipeline)
625 {
626 stub_return(VK_UNSUPPORTED);
627 }
628
629 // Pipeline layout functions
630
631 VkResult anv_CreatePipelineLayout(
632 VkDevice _device,
633 const VkPipelineLayoutCreateInfo* pCreateInfo,
634 VkPipelineLayout* pPipelineLayout)
635 {
636 struct anv_device *device = (struct anv_device *) _device;
637 struct anv_pipeline_layout *layout;
638
639 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO);
640
641 layout = anv_device_alloc(device, sizeof(*layout), 8,
642 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
643 if (layout == NULL)
644 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
645
646 layout->num_sets = pCreateInfo->descriptorSetCount;
647
648 uint32_t surface_start[VK_NUM_SHADER_STAGE] = { 0, };
649 uint32_t sampler_start[VK_NUM_SHADER_STAGE] = { 0, };
650
651 for (uint32_t s = 0; s < VK_NUM_SHADER_STAGE; s++) {
652 layout->stage[s].surface_count = 0;
653 layout->stage[s].sampler_count = 0;
654 }
655
656 for (uint32_t i = 0; i < pCreateInfo->descriptorSetCount; i++) {
657 struct anv_descriptor_set_layout *set_layout =
658 (struct anv_descriptor_set_layout *) pCreateInfo->pSetLayouts[i];
659
660 layout->set[i].layout = set_layout;
661 for (uint32_t s = 0; s < VK_NUM_SHADER_STAGE; s++) {
662 layout->set[i].surface_start[s] = surface_start[s];
663 surface_start[s] += set_layout->stage[s].surface_count;
664 layout->set[i].sampler_start[s] = sampler_start[s];
665 sampler_start[s] += set_layout->stage[s].sampler_count;
666
667 layout->stage[s].surface_count += set_layout->stage[s].surface_count;
668 layout->stage[s].sampler_count += set_layout->stage[s].sampler_count;
669 }
670 }
671
672 *pPipelineLayout = (VkPipelineLayout) layout;
673
674 return VK_SUCCESS;
675 }