2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 VkResult
anv_CreateShader(
36 const VkShaderCreateInfo
* pCreateInfo
,
39 struct anv_device
*device
= (struct anv_device
*) _device
;
40 struct anv_shader
*shader
;
42 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_CREATE_INFO
);
44 shader
= anv_device_alloc(device
, sizeof(*shader
) + pCreateInfo
->codeSize
, 8,
45 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
47 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
49 shader
->size
= pCreateInfo
->codeSize
;
50 memcpy(shader
->data
, pCreateInfo
->pCode
, shader
->size
);
52 *pShader
= (VkShader
) shader
;
60 emit_vertex_input(struct anv_pipeline
*pipeline
, VkPipelineVertexInputCreateInfo
*info
)
62 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
64 bool instancing_enable
[32];
66 pipeline
->vb_used
= 0;
67 for (uint32_t i
= 0; i
< info
->bindingCount
; i
++) {
68 const VkVertexInputBindingDescription
*desc
=
69 &info
->pVertexBindingDescriptions
[i
];
71 pipeline
->vb_used
|= 1 << desc
->binding
;
72 pipeline
->binding_stride
[desc
->binding
] = desc
->strideInBytes
;
74 /* Step rate is programmed per vertex element (attribute), not
75 * binding. Set up a map of which bindings step per instance, for
76 * reference by vertex element setup. */
77 switch (desc
->stepRate
) {
79 case VK_VERTEX_INPUT_STEP_RATE_VERTEX
:
80 instancing_enable
[desc
->binding
] = false;
82 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE
:
83 instancing_enable
[desc
->binding
] = true;
88 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
89 GEN8_3DSTATE_VERTEX_ELEMENTS
);
91 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
92 const VkVertexInputAttributeDescription
*desc
=
93 &info
->pVertexAttributeDescriptions
[i
];
94 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
96 struct GEN8_VERTEX_ELEMENT_STATE element
= {
97 .VertexBufferIndex
= desc
->binding
,
99 .SourceElementFormat
= format
->format
,
100 .EdgeFlagEnable
= false,
101 .SourceElementOffset
= desc
->offsetInBytes
,
102 .Component0Control
= VFCOMP_STORE_SRC
,
103 .Component1Control
= format
->channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
104 .Component2Control
= format
->channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
105 .Component3Control
= format
->channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
107 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
109 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
110 .InstancingEnable
= instancing_enable
[desc
->binding
],
111 .VertexElementIndex
= i
,
112 /* Vulkan so far doesn't have an instance divisor, so
113 * this is always 1 (ignored if not instancing). */
114 .InstanceDataStepRate
= 1);
117 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
118 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
119 .VertexIDComponentNumber
= 2,
120 .VertexIDElementOffset
= info
->bindingCount
,
121 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
122 .InstanceIDComponentNumber
= 3,
123 .InstanceIDElementOffset
= info
->bindingCount
);
127 emit_ia_state(struct anv_pipeline
*pipeline
,
128 VkPipelineIaStateCreateInfo
*info
,
129 const struct anv_pipeline_create_info
*extra
)
131 static const uint32_t vk_to_gen_primitive_type
[] = {
132 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
133 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
134 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
135 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
136 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
137 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
138 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ
] = _3DPRIM_LINELIST_ADJ
,
139 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ
] = _3DPRIM_LISTSTRIP_ADJ
,
140 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ
] = _3DPRIM_TRILIST_ADJ
,
141 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ
] = _3DPRIM_TRISTRIP_ADJ
,
142 [VK_PRIMITIVE_TOPOLOGY_PATCH
] = _3DPRIM_PATCHLIST_1
144 uint32_t topology
= vk_to_gen_primitive_type
[info
->topology
];
146 if (extra
&& extra
->use_rectlist
)
147 topology
= _3DPRIM_RECTLIST
;
149 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF
,
150 .IndexedDrawCutIndexEnable
= info
->primitiveRestartEnable
,
151 .CutIndex
= info
->primitiveRestartIndex
);
152 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
153 .PrimitiveTopologyType
= topology
);
157 emit_rs_state(struct anv_pipeline
*pipeline
, VkPipelineRsStateCreateInfo
*info
,
158 const struct anv_pipeline_create_info
*extra
)
160 static const uint32_t vk_to_gen_cullmode
[] = {
161 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
162 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
163 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
164 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
167 static const uint32_t vk_to_gen_fillmode
[] = {
168 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
169 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
170 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
173 static const uint32_t vk_to_gen_front_face
[] = {
174 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
175 [VK_FRONT_FACE_CW
] = Clockwise
178 static const uint32_t vk_to_gen_coordinate_origin
[] = {
179 [VK_COORDINATE_ORIGIN_UPPER_LEFT
] = UPPERLEFT
,
180 [VK_COORDINATE_ORIGIN_LOWER_LEFT
] = LOWERLEFT
183 struct GEN8_3DSTATE_SF sf
= {
184 GEN8_3DSTATE_SF_header
,
185 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
186 .TriangleStripListProvokingVertexSelect
=
187 info
->provokingVertex
== VK_PROVOKING_VERTEX_FIRST
? 0 : 2,
188 .LineStripListProvokingVertexSelect
=
189 info
->provokingVertex
== VK_PROVOKING_VERTEX_FIRST
? 0 : 1,
190 .TriangleFanProvokingVertexSelect
=
191 info
->provokingVertex
== VK_PROVOKING_VERTEX_FIRST
? 0 : 2,
192 .PointWidthSource
= info
->programPointSize
? Vertex
: State
,
195 /* FINISHME: bool32_t rasterizerDiscardEnable; */
197 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->state_sf
, &sf
);
199 struct GEN8_3DSTATE_RASTER raster
= {
200 GEN8_3DSTATE_RASTER_header
,
201 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
202 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
203 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
204 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
205 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
206 .ViewportZClipTestEnable
= info
->depthClipEnable
209 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->state_raster
, &raster
);
211 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
212 .ForceVertexURBEntryReadLength
= false,
213 .ForceVertexURBEntryReadOffset
= false,
214 .PointSpriteTextureCoordinateOrigin
=
215 vk_to_gen_coordinate_origin
[info
->pointOrigin
],
216 .NumberofSFOutputAttributes
=
217 pipeline
->wm_prog_data
.num_varying_inputs
);
222 emit_cb_state(struct anv_pipeline
*pipeline
, VkPipelineCbStateCreateInfo
*info
)
224 struct anv_device
*device
= pipeline
->device
;
226 static const uint32_t vk_to_gen_logic_op
[] = {
227 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
228 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
229 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
230 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
231 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
232 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
233 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
234 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
235 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
236 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
237 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
238 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
239 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
240 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
241 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
242 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
245 static const uint32_t vk_to_gen_blend
[] = {
246 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
247 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
248 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
249 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
250 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
251 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
252 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
253 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
254 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
255 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
256 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
257 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
258 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
259 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
260 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
261 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
262 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
263 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
264 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
267 static const uint32_t vk_to_gen_blend_op
[] = {
268 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
269 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
270 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
271 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
272 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
275 uint32_t num_dwords
= 1 + info
->attachmentCount
* 2;
276 pipeline
->blend_state
=
277 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
279 struct GEN8_BLEND_STATE blend_state
= {
280 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
283 uint32_t *state
= pipeline
->blend_state
.map
;
284 GEN8_BLEND_STATE_pack(NULL
, state
, &blend_state
);
286 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
287 const VkPipelineCbAttachmentState
*a
= &info
->pAttachments
[i
];
289 struct GEN8_BLEND_STATE_ENTRY entry
= {
290 .LogicOpEnable
= info
->logicOpEnable
,
291 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
292 .ColorBufferBlendEnable
= a
->blendEnable
,
293 .PreBlendSourceOnlyClampEnable
= false,
294 .PreBlendColorClampEnable
= false,
295 .PostBlendColorClampEnable
= false,
296 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
297 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
298 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
299 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
300 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
301 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
302 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
303 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
304 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
305 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
308 GEN8_BLEND_STATE_ENTRY_pack(NULL
, state
+ i
* 2 + 1, &entry
);
311 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
312 .BlendStatePointer
= pipeline
->blend_state
.offset
,
313 .BlendStatePointerValid
= true);
316 static const uint32_t vk_to_gen_compare_op
[] = {
317 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
318 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
319 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
320 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
321 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
322 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
323 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
324 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
327 static const uint32_t vk_to_gen_stencil_op
[] = {
328 [VK_STENCIL_OP_KEEP
] = 0,
329 [VK_STENCIL_OP_ZERO
] = 0,
330 [VK_STENCIL_OP_REPLACE
] = 0,
331 [VK_STENCIL_OP_INC_CLAMP
] = 0,
332 [VK_STENCIL_OP_DEC_CLAMP
] = 0,
333 [VK_STENCIL_OP_INVERT
] = 0,
334 [VK_STENCIL_OP_INC_WRAP
] = 0,
335 [VK_STENCIL_OP_DEC_WRAP
] = 0
339 emit_ds_state(struct anv_pipeline
*pipeline
, VkPipelineDsStateCreateInfo
*info
)
341 /* bool32_t depthBoundsEnable; // optional (depth_bounds_test) */
343 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
344 .DepthTestEnable
= info
->depthTestEnable
,
345 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
346 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
347 .DoubleSidedStencilEnable
= true,
349 .StencilTestEnable
= info
->stencilTestEnable
,
350 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
351 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
352 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
353 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
354 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
355 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
356 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
357 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
360 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->state_wm_depth_stencil
, &wm_depth_stencil
);
363 VkResult
anv_CreateGraphicsPipeline(
365 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
366 VkPipeline
* pPipeline
)
368 return anv_pipeline_create(device
, pCreateInfo
, NULL
, pPipeline
);
372 anv_pipeline_destroy(struct anv_device
*device
,
373 struct anv_object
*object
,
374 VkObjectType obj_type
)
376 struct anv_pipeline
*pipeline
= (struct anv_pipeline
*) object
;
378 assert(obj_type
== VK_OBJECT_TYPE_PIPELINE
);
380 anv_compiler_free(pipeline
);
381 anv_batch_finish(&pipeline
->batch
, pipeline
->device
);
382 anv_device_free(pipeline
->device
, pipeline
);
388 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
389 const struct anv_pipeline_create_info
* extra
,
390 VkPipeline
* pPipeline
)
392 struct anv_device
*device
= (struct anv_device
*) _device
;
393 struct anv_pipeline
*pipeline
;
394 const struct anv_common
*common
;
395 VkPipelineShaderStageCreateInfo
*shader_create_info
;
396 VkPipelineIaStateCreateInfo
*ia_info
= NULL
;
397 VkPipelineRsStateCreateInfo
*rs_info
= NULL
;
398 VkPipelineDsStateCreateInfo
*ds_info
= NULL
;
399 VkPipelineCbStateCreateInfo
*cb_info
= NULL
;
400 VkPipelineVertexInputCreateInfo
*vi_info
;
402 uint32_t offset
, length
;
404 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
406 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
407 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
408 if (pipeline
== NULL
)
409 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
411 pipeline
->base
.destructor
= anv_pipeline_destroy
;
412 pipeline
->device
= device
;
413 pipeline
->layout
= (struct anv_pipeline_layout
*) pCreateInfo
->layout
;
414 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
415 result
= anv_batch_init(&pipeline
->batch
, device
);
416 if (result
!= VK_SUCCESS
)
419 anv_state_stream_init(&pipeline
->program_stream
,
420 &device
->instruction_block_pool
);
422 for (common
= pCreateInfo
->pNext
; common
; common
= common
->pNext
) {
423 switch (common
->sType
) {
424 case VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_CREATE_INFO
:
425 vi_info
= (VkPipelineVertexInputCreateInfo
*) common
;
427 case VK_STRUCTURE_TYPE_PIPELINE_IA_STATE_CREATE_INFO
:
428 ia_info
= (VkPipelineIaStateCreateInfo
*) common
;
430 case VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO
:
431 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO");
433 case VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO
:
434 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO");
436 case VK_STRUCTURE_TYPE_PIPELINE_RS_STATE_CREATE_INFO
:
437 rs_info
= (VkPipelineRsStateCreateInfo
*) common
;
439 case VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO
:
440 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO");
442 case VK_STRUCTURE_TYPE_PIPELINE_CB_STATE_CREATE_INFO
:
443 cb_info
= (VkPipelineCbStateCreateInfo
*) common
;
445 case VK_STRUCTURE_TYPE_PIPELINE_DS_STATE_CREATE_INFO
:
446 ds_info
= (VkPipelineDsStateCreateInfo
*) common
;
448 case VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
:
449 shader_create_info
= (VkPipelineShaderStageCreateInfo
*) common
;
450 pipeline
->shaders
[shader_create_info
->shader
.stage
] =
451 (struct anv_shader
*) shader_create_info
->shader
.shader
;
458 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
460 anv_compiler_run(device
->compiler
, pipeline
);
462 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
463 * hard code this to num_attributes - 2. This is because the attributes
464 * include VUE header and position, which aren't counted as varying
466 if (pipeline
->vs_simd8
== NO_KERNEL
)
467 pipeline
->wm_prog_data
.num_varying_inputs
= vi_info
->attributeCount
- 2;
470 emit_vertex_input(pipeline
, vi_info
);
472 emit_ia_state(pipeline
, ia_info
, extra
);
474 emit_rs_state(pipeline
, rs_info
, extra
);
475 /* ds_info is optional if we're not using depth or stencil buffers, ps is
476 * optional for depth-only rendering. */
478 emit_ds_state(pipeline
, ds_info
);
480 emit_cb_state(pipeline
, cb_info
);
482 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
484 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
));
486 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
487 .StatisticsEnable
= true,
488 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
489 .LineAntialiasingRegionWidth
= _10pixels
,
490 .EarlyDepthStencilControl
= NORMAL
,
491 .ForceThreadDispatchEnable
= NORMAL
,
492 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
493 .BarycentricInterpolationMode
=
494 pipeline
->wm_prog_data
.barycentric_interp_modes
);
496 uint32_t samples
= 1;
497 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
498 bool enable_sampling
= samples
> 1 ? true : false;
500 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
501 .PixelPositionOffsetEnable
= enable_sampling
,
502 .PixelLocation
= CENTER
,
503 .NumberofMultisamples
= log2_samples
);
505 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
506 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
507 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
508 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
510 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
511 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
512 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
513 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
515 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
516 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
517 .HSURBEntryAllocationSize
= 0,
518 .HSNumberofURBEntries
= 0);
520 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
521 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
522 .DSURBEntryAllocationSize
= 0,
523 .DSNumberofURBEntries
= 0);
525 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
527 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
529 if (pipeline
->gs_vec4
== NO_KERNEL
)
530 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
532 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
533 .SingleProgramFlow
= false,
534 .KernelStartPointer
= pipeline
->gs_vec4
,
535 .VectorMaskEnable
= Vmask
,
537 .BindingTableEntryCount
= 0,
538 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
540 .PerThreadScratchSpace
= 0,
541 .ScratchSpaceBasePointer
= 0,
543 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
544 .OutputTopology
= gs_prog_data
->output_topology
,
545 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
546 .DispatchGRFStartRegisterForURBData
=
547 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
549 .MaximumNumberofThreads
= device
->info
.max_gs_threads
,
550 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
551 //pipeline->gs_prog_data.dispatch_mode |
552 .StatisticsEnable
= true,
553 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
554 .ReorderMode
= TRAILING
,
557 .ControlDataFormat
= gs_prog_data
->control_data_format
,
559 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
560 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
561 * UserClipDistanceCullTestEnableBitmask(v)
564 .VertexURBEntryOutputReadOffset
= offset
,
565 .VertexURBEntryOutputLength
= length
);
567 //trp_generate_blend_hw_cmds(batch, pipeline);
569 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
570 /* Skip the VUE header and position slots */
572 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
574 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
575 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
576 .FunctionEnable
= false,
577 .VertexURBEntryOutputReadOffset
= 1,
578 /* Even if VS is disabled, SBE still gets the amount of
579 * vertex data to read from this field. We use attribute
580 * count - 1, as we don't count the VUE header here. */
581 .VertexURBEntryOutputLength
=
582 DIV_ROUND_UP(vi_info
->attributeCount
- 1, 2));
584 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
585 .KernelStartPointer
= pipeline
->vs_simd8
,
586 .SingleVertexDispatch
= Multiple
,
587 .VectorMaskEnable
= Dmask
,
589 .BindingTableEntryCount
=
590 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
591 .ThreadDispatchPriority
= Normal
,
592 .FloatingPointMode
= IEEE754
,
593 .IllegalOpcodeExceptionEnable
= false,
594 .AccessesUAV
= false,
595 .SoftwareExceptionEnable
= false,
597 /* FIXME: pointer needs to be assigned outside as it aliases
598 * PerThreadScratchSpace.
600 .ScratchSpaceBasePointer
= 0,
601 .PerThreadScratchSpace
= 0,
603 .DispatchGRFStartRegisterForURBData
=
604 vue_prog_data
->base
.dispatch_grf_start_reg
,
605 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
606 .VertexURBEntryReadOffset
= 0,
608 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
609 .StatisticsEnable
= false,
610 .SIMD8DispatchEnable
= true,
611 .VertexCacheDisable
= ia_info
->disableVertexReuse
,
612 .FunctionEnable
= true,
614 .VertexURBEntryOutputReadOffset
= offset
,
615 .VertexURBEntryOutputLength
= length
,
616 .UserClipDistanceClipTestEnableBitmask
= 0,
617 .UserClipDistanceCullTestEnableBitmask
= 0);
619 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
620 uint32_t ksp0
, ksp2
, grf_start0
, grf_start2
;
624 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
625 ksp0
= pipeline
->ps_simd8
;
626 grf_start0
= wm_prog_data
->base
.dispatch_grf_start_reg
;
627 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
628 ksp2
= pipeline
->ps_simd16
;
629 grf_start2
= wm_prog_data
->dispatch_grf_start_reg_16
;
631 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
632 ksp0
= pipeline
->ps_simd16
;
633 grf_start0
= wm_prog_data
->dispatch_grf_start_reg_16
;
635 unreachable("no ps shader");
638 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
639 .KernelStartPointer0
= ksp0
,
641 .SingleProgramFlow
= false,
642 .VectorMaskEnable
= true,
645 .ScratchSpaceBasePointer
= 0,
646 .PerThreadScratchSpace
= 0,
648 .MaximumNumberofThreadsPerPSD
= 64 - 2,
649 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
650 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
651 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
652 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
653 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
654 ._32PixelDispatchEnable
= false,
656 .DispatchGRFStartRegisterForConstantSetupData0
= grf_start0
,
657 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
658 .DispatchGRFStartRegisterForConstantSetupData2
= grf_start2
,
660 .KernelStartPointer1
= 0,
661 .KernelStartPointer2
= ksp2
);
663 bool per_sample_ps
= false;
664 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
665 .PixelShaderValid
= true,
666 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
667 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
668 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
669 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
670 .PixelShaderIsPerSample
= per_sample_ps
);
672 *pPipeline
= (VkPipeline
) pipeline
;
677 anv_device_free(device
, pipeline
);
682 VkResult
anv_CreateGraphicsPipelineDerivative(
684 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
685 VkPipeline basePipeline
,
686 VkPipeline
* pPipeline
)
688 stub_return(VK_UNSUPPORTED
);
691 VkResult
anv_CreateComputePipeline(
693 const VkComputePipelineCreateInfo
* pCreateInfo
,
694 VkPipeline
* pPipeline
)
696 stub_return(VK_UNSUPPORTED
);
699 VkResult
anv_StorePipeline(
705 stub_return(VK_UNSUPPORTED
);
708 VkResult
anv_LoadPipeline(
712 VkPipeline
* pPipeline
)
714 stub_return(VK_UNSUPPORTED
);
717 VkResult
anv_LoadPipelineDerivative(
721 VkPipeline basePipeline
,
722 VkPipeline
* pPipeline
)
724 stub_return(VK_UNSUPPORTED
);
727 // Pipeline layout functions
729 VkResult
anv_CreatePipelineLayout(
731 const VkPipelineLayoutCreateInfo
* pCreateInfo
,
732 VkPipelineLayout
* pPipelineLayout
)
734 struct anv_device
*device
= (struct anv_device
*) _device
;
735 struct anv_pipeline_layout
*layout
;
737 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
);
739 layout
= anv_device_alloc(device
, sizeof(*layout
), 8,
740 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
742 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
744 layout
->num_sets
= pCreateInfo
->descriptorSetCount
;
746 uint32_t surface_start
[VK_NUM_SHADER_STAGE
] = { 0, };
747 uint32_t sampler_start
[VK_NUM_SHADER_STAGE
] = { 0, };
749 for (uint32_t s
= 0; s
< VK_NUM_SHADER_STAGE
; s
++) {
750 layout
->stage
[s
].surface_count
= 0;
751 layout
->stage
[s
].sampler_count
= 0;
754 for (uint32_t i
= 0; i
< pCreateInfo
->descriptorSetCount
; i
++) {
755 struct anv_descriptor_set_layout
*set_layout
=
756 (struct anv_descriptor_set_layout
*) pCreateInfo
->pSetLayouts
[i
];
758 layout
->set
[i
].layout
= set_layout
;
759 for (uint32_t s
= 0; s
< VK_NUM_SHADER_STAGE
; s
++) {
760 layout
->set
[i
].surface_start
[s
] = surface_start
[s
];
761 surface_start
[s
] += set_layout
->stage
[s
].surface_count
;
762 layout
->set
[i
].sampler_start
[s
] = sampler_start
[s
];
763 sampler_start
[s
] += set_layout
->stage
[s
].sampler_count
;
765 layout
->stage
[s
].surface_count
+= set_layout
->stage
[s
].surface_count
;
766 layout
->stage
[s
].sampler_count
+= set_layout
->stage
[s
].sampler_count
;
770 *pPipelineLayout
= (VkPipelineLayout
) layout
;