vk/pipeline: Use a state_stream for storing programs
[mesa.git] / src / vulkan / pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "private.h"
31
32 // Shader functions
33
34 VkResult anv_CreateShader(
35 VkDevice _device,
36 const VkShaderCreateInfo* pCreateInfo,
37 VkShader* pShader)
38 {
39 struct anv_device *device = (struct anv_device *) _device;
40 struct anv_shader *shader;
41
42 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_CREATE_INFO);
43
44 shader = anv_device_alloc(device, sizeof(*shader) + pCreateInfo->codeSize, 8,
45 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
46 if (shader == NULL)
47 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
48
49 shader->size = pCreateInfo->codeSize;
50 memcpy(shader->data, pCreateInfo->pCode, shader->size);
51
52 *pShader = (VkShader) shader;
53
54 return VK_SUCCESS;
55 }
56
57 // Pipeline functions
58
59 static void
60 emit_vertex_input(struct anv_pipeline *pipeline, VkPipelineVertexInputCreateInfo *info)
61 {
62 const uint32_t num_dwords = 1 + info->attributeCount * 2;
63 uint32_t *p;
64 bool instancing_enable[32];
65
66 for (uint32_t i = 0; i < info->bindingCount; i++) {
67 const VkVertexInputBindingDescription *desc =
68 &info->pVertexBindingDescriptions[i];
69
70 pipeline->binding_stride[desc->binding] = desc->strideInBytes;
71
72 /* Step rate is programmed per vertex element (attribute), not
73 * binding. Set up a map of which bindings step per instance, for
74 * reference by vertex element setup. */
75 switch (desc->stepRate) {
76 default:
77 case VK_VERTEX_INPUT_STEP_RATE_VERTEX:
78 instancing_enable[desc->binding] = false;
79 break;
80 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE:
81 instancing_enable[desc->binding] = true;
82 break;
83 }
84 }
85
86 p = anv_batch_emitn(&pipeline->batch, num_dwords,
87 GEN8_3DSTATE_VERTEX_ELEMENTS);
88
89 for (uint32_t i = 0; i < info->attributeCount; i++) {
90 const VkVertexInputAttributeDescription *desc =
91 &info->pVertexAttributeDescriptions[i];
92 const struct anv_format *format = anv_format_for_vk_format(desc->format);
93
94 struct GEN8_VERTEX_ELEMENT_STATE element = {
95 .VertexBufferIndex = desc->binding,
96 .Valid = true,
97 .SourceElementFormat = format->format,
98 .EdgeFlagEnable = false,
99 .SourceElementOffset = desc->offsetInBytes,
100 .Component0Control = VFCOMP_STORE_SRC,
101 .Component1Control = format->channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
102 .Component2Control = format->channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
103 .Component3Control = format->channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
104 };
105 GEN8_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
106
107 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_INSTANCING,
108 .InstancingEnable = instancing_enable[desc->binding],
109 .VertexElementIndex = i,
110 /* Vulkan so far doesn't have an instance divisor, so
111 * this is always 1 (ignored if not instancing). */
112 .InstanceDataStepRate = 1);
113 }
114
115 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_SGVS,
116 .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
117 .VertexIDComponentNumber = 2,
118 .VertexIDElementOffset = info->bindingCount,
119 .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
120 .InstanceIDComponentNumber = 3,
121 .InstanceIDElementOffset = info->bindingCount);
122 }
123
124 static void
125 emit_ia_state(struct anv_pipeline *pipeline,
126 VkPipelineIaStateCreateInfo *info,
127 const struct anv_pipeline_create_info *extra)
128 {
129 static const uint32_t vk_to_gen_primitive_type[] = {
130 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
131 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
132 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
133 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
134 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
135 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
136 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ] = _3DPRIM_LINELIST_ADJ,
137 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ] = _3DPRIM_LISTSTRIP_ADJ,
138 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ] = _3DPRIM_TRILIST_ADJ,
139 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ] = _3DPRIM_TRISTRIP_ADJ,
140 [VK_PRIMITIVE_TOPOLOGY_PATCH] = _3DPRIM_PATCHLIST_1
141 };
142 uint32_t topology = vk_to_gen_primitive_type[info->topology];
143
144 if (extra && extra->use_rectlist)
145 topology = _3DPRIM_RECTLIST;
146
147 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF,
148 .IndexedDrawCutIndexEnable = info->primitiveRestartEnable,
149 .CutIndex = info->primitiveRestartIndex);
150 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_TOPOLOGY,
151 .PrimitiveTopologyType = topology);
152 }
153
154 static void
155 emit_rs_state(struct anv_pipeline *pipeline, VkPipelineRsStateCreateInfo *info,
156 const struct anv_pipeline_create_info *extra)
157
158 {
159 static const uint32_t vk_to_gen_cullmode[] = {
160 [VK_CULL_MODE_NONE] = CULLMODE_NONE,
161 [VK_CULL_MODE_FRONT] = CULLMODE_FRONT,
162 [VK_CULL_MODE_BACK] = CULLMODE_BACK,
163 [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
164 };
165
166 static const uint32_t vk_to_gen_fillmode[] = {
167 [VK_FILL_MODE_POINTS] = RASTER_POINT,
168 [VK_FILL_MODE_WIREFRAME] = RASTER_WIREFRAME,
169 [VK_FILL_MODE_SOLID] = RASTER_SOLID
170 };
171
172 static const uint32_t vk_to_gen_front_face[] = {
173 [VK_FRONT_FACE_CCW] = CounterClockwise,
174 [VK_FRONT_FACE_CW] = Clockwise
175 };
176
177 static const uint32_t vk_to_gen_coordinate_origin[] = {
178 [VK_COORDINATE_ORIGIN_UPPER_LEFT] = UPPERLEFT,
179 [VK_COORDINATE_ORIGIN_LOWER_LEFT] = LOWERLEFT
180 };
181
182 struct GEN8_3DSTATE_SF sf = {
183 GEN8_3DSTATE_SF_header,
184 .ViewportTransformEnable = !(extra && extra->disable_viewport),
185 .TriangleStripListProvokingVertexSelect =
186 info->provokingVertex == VK_PROVOKING_VERTEX_FIRST ? 0 : 2,
187 .LineStripListProvokingVertexSelect =
188 info->provokingVertex == VK_PROVOKING_VERTEX_FIRST ? 0 : 1,
189 .TriangleFanProvokingVertexSelect =
190 info->provokingVertex == VK_PROVOKING_VERTEX_FIRST ? 0 : 2,
191 .PointWidthSource = info->programPointSize ? Vertex : State,
192 };
193
194 /* bool32_t rasterizerDiscardEnable; */
195
196
197 GEN8_3DSTATE_SF_pack(NULL, pipeline->state_sf, &sf);
198
199 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_RASTER,
200 .FrontWinding = vk_to_gen_front_face[info->frontFace],
201 .CullMode = vk_to_gen_cullmode[info->cullMode],
202 .FrontFaceFillMode = vk_to_gen_fillmode[info->fillMode],
203 .BackFaceFillMode = vk_to_gen_fillmode[info->fillMode],
204 .ScissorRectangleEnable = !(extra && extra->disable_scissor),
205 .ViewportZClipTestEnable = info->depthClipEnable);
206
207 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_SBE,
208 .ForceVertexURBEntryReadLength = false,
209 .ForceVertexURBEntryReadOffset = false,
210 .PointSpriteTextureCoordinateOrigin =
211 vk_to_gen_coordinate_origin[info->pointOrigin],
212 .NumberofSFOutputAttributes =
213 pipeline->wm_prog_data.num_varying_inputs);
214
215 }
216
217 VkResult anv_CreateGraphicsPipeline(
218 VkDevice device,
219 const VkGraphicsPipelineCreateInfo* pCreateInfo,
220 VkPipeline* pPipeline)
221 {
222 return anv_pipeline_create(device, pCreateInfo, NULL, pPipeline);
223 }
224
225
226 VkResult
227 anv_pipeline_create(
228 VkDevice _device,
229 const VkGraphicsPipelineCreateInfo* pCreateInfo,
230 const struct anv_pipeline_create_info * extra,
231 VkPipeline* pPipeline)
232 {
233 struct anv_device *device = (struct anv_device *) _device;
234 struct anv_pipeline *pipeline;
235 const struct anv_common *common;
236 VkPipelineShaderStageCreateInfo *shader_create_info;
237 VkPipelineIaStateCreateInfo *ia_info;
238 VkPipelineRsStateCreateInfo *rs_info;
239 VkPipelineVertexInputCreateInfo *vi_info;
240 VkResult result;
241 uint32_t offset, length;
242
243 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
244
245 pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
246 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
247 if (pipeline == NULL)
248 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
249
250 pipeline->device = device;
251 pipeline->layout = (struct anv_pipeline_layout *) pCreateInfo->layout;
252 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
253 result = anv_batch_init(&pipeline->batch, device);
254 if (result != VK_SUCCESS)
255 goto fail;
256
257 anv_state_stream_init(&pipeline->program_stream,
258 &device->instruction_block_pool);
259
260 for (common = pCreateInfo->pNext; common; common = common->pNext) {
261 switch (common->sType) {
262 case VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_CREATE_INFO:
263 vi_info = (VkPipelineVertexInputCreateInfo *) common;
264 break;
265 case VK_STRUCTURE_TYPE_PIPELINE_IA_STATE_CREATE_INFO:
266 ia_info = (VkPipelineIaStateCreateInfo *) common;
267 break;
268 case VK_STRUCTURE_TYPE_PIPELINE_TESS_STATE_CREATE_INFO:
269 case VK_STRUCTURE_TYPE_PIPELINE_VP_STATE_CREATE_INFO:
270 break;
271 case VK_STRUCTURE_TYPE_PIPELINE_RS_STATE_CREATE_INFO:
272 rs_info = (VkPipelineRsStateCreateInfo *) common;
273 break;
274 case VK_STRUCTURE_TYPE_PIPELINE_MS_STATE_CREATE_INFO:
275 case VK_STRUCTURE_TYPE_PIPELINE_CB_STATE_CREATE_INFO:
276 case VK_STRUCTURE_TYPE_PIPELINE_DS_STATE_CREATE_INFO:
277 case VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO:
278 shader_create_info = (VkPipelineShaderStageCreateInfo *) common;
279 pipeline->shaders[shader_create_info->shader.stage] =
280 (struct anv_shader *) shader_create_info->shader.shader;
281 break;
282 default:
283 break;
284 }
285 }
286
287 pipeline->use_repclear = extra && extra->use_repclear;
288
289 anv_compiler_run(device->compiler, pipeline);
290
291 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
292 * hard code this to num_attributes - 2. This is because the attributes
293 * include VUE header and position, which aren't counted as varying
294 * inputs. */
295 if (pipeline->vs_simd8 == NO_KERNEL)
296 pipeline->wm_prog_data.num_varying_inputs = vi_info->attributeCount - 2;
297
298 emit_vertex_input(pipeline, vi_info);
299 emit_ia_state(pipeline, ia_info, extra);
300 emit_rs_state(pipeline, rs_info, extra);
301
302 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_CLIP,
303 .ClipEnable = true,
304 .ViewportXYClipTestEnable = !(extra && extra->disable_viewport));
305
306 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_WM,
307 .StatisticsEnable = true,
308 .LineEndCapAntialiasingRegionWidth = _05pixels,
309 .LineAntialiasingRegionWidth = _10pixels,
310 .EarlyDepthStencilControl = NORMAL,
311 .ForceThreadDispatchEnable = NORMAL,
312 .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
313 .BarycentricInterpolationMode =
314 pipeline->wm_prog_data.barycentric_interp_modes);
315
316 uint32_t samples = 1;
317 uint32_t log2_samples = __builtin_ffs(samples) - 1;
318 bool enable_sampling = samples > 1 ? true : false;
319
320 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_MULTISAMPLE,
321 .PixelPositionOffsetEnable = enable_sampling,
322 .PixelLocation = CENTER,
323 .NumberofMultisamples = log2_samples);
324
325 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_VS,
326 .VSURBStartingAddress = pipeline->urb.vs_start,
327 .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
328 .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
329
330 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_GS,
331 .GSURBStartingAddress = pipeline->urb.gs_start,
332 .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
333 .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
334
335 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_HS,
336 .HSURBStartingAddress = pipeline->urb.vs_start,
337 .HSURBEntryAllocationSize = 0,
338 .HSNumberofURBEntries = 0);
339
340 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_DS,
341 .DSURBStartingAddress = pipeline->urb.vs_start,
342 .DSURBEntryAllocationSize = 0,
343 .DSNumberofURBEntries = 0);
344
345 const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
346 offset = 1;
347 length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
348
349 if (pipeline->gs_vec4 == NO_KERNEL)
350 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_GS, .Enable = false);
351 else
352 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_GS,
353 .SingleProgramFlow = false,
354 .KernelStartPointer = pipeline->gs_vec4,
355 .VectorMaskEnable = Vmask,
356 .SamplerCount = 0,
357 .BindingTableEntryCount = 0,
358 .ExpectedVertexCount = pipeline->gs_vertex_count,
359
360 .PerThreadScratchSpace = 0,
361 .ScratchSpaceBasePointer = 0,
362
363 .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
364 .OutputTopology = gs_prog_data->output_topology,
365 .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
366 .DispatchGRFStartRegisterForURBData =
367 gs_prog_data->base.base.dispatch_grf_start_reg,
368
369 .MaximumNumberofThreads = device->info.max_gs_threads,
370 .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
371 //pipeline->gs_prog_data.dispatch_mode |
372 .StatisticsEnable = true,
373 .IncludePrimitiveID = gs_prog_data->include_primitive_id,
374 .ReorderMode = TRAILING,
375 .Enable = true,
376
377 .ControlDataFormat = gs_prog_data->control_data_format,
378
379 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
380 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
381 * UserClipDistanceCullTestEnableBitmask(v)
382 */
383
384 .VertexURBEntryOutputReadOffset = offset,
385 .VertexURBEntryOutputLength = length);
386
387 //trp_generate_blend_hw_cmds(batch, pipeline);
388
389 const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
390 /* Skip the VUE header and position slots */
391 offset = 1;
392 length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
393
394 if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
395 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VS,
396 .FunctionEnable = false,
397 .VertexURBEntryOutputReadOffset = 1,
398 /* Even if VS is disabled, SBE still gets the amount of
399 * vertex data to read from this field. We use attribute
400 * count - 1, as we don't count the VUE header here. */
401 .VertexURBEntryOutputLength =
402 DIV_ROUND_UP(vi_info->attributeCount - 1, 2));
403 else
404 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VS,
405 .KernelStartPointer = pipeline->vs_simd8,
406 .SingleVertexDispatch = Multiple,
407 .VectorMaskEnable = Dmask,
408 .SamplerCount = 0,
409 .BindingTableEntryCount =
410 vue_prog_data->base.binding_table.size_bytes / 4,
411 .ThreadDispatchPriority = Normal,
412 .FloatingPointMode = IEEE754,
413 .IllegalOpcodeExceptionEnable = false,
414 .AccessesUAV = false,
415 .SoftwareExceptionEnable = false,
416
417 /* FIXME: pointer needs to be assigned outside as it aliases
418 * PerThreadScratchSpace.
419 */
420 .ScratchSpaceBasePointer = 0,
421 .PerThreadScratchSpace = 0,
422
423 .DispatchGRFStartRegisterForURBData =
424 vue_prog_data->base.dispatch_grf_start_reg,
425 .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
426 .VertexURBEntryReadOffset = 0,
427
428 .MaximumNumberofThreads = device->info.max_vs_threads - 1,
429 .StatisticsEnable = false,
430 .SIMD8DispatchEnable = true,
431 .VertexCacheDisable = ia_info->disableVertexReuse,
432 .FunctionEnable = true,
433
434 .VertexURBEntryOutputReadOffset = offset,
435 .VertexURBEntryOutputLength = length,
436 .UserClipDistanceClipTestEnableBitmask = 0,
437 .UserClipDistanceCullTestEnableBitmask = 0);
438
439 const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
440 uint32_t ksp0, ksp2, grf_start0, grf_start2;
441
442 ksp2 = 0;
443 grf_start2 = 0;
444 if (pipeline->ps_simd8 != NO_KERNEL) {
445 ksp0 = pipeline->ps_simd8;
446 grf_start0 = wm_prog_data->base.dispatch_grf_start_reg;
447 if (pipeline->ps_simd16 != NO_KERNEL) {
448 ksp2 = pipeline->ps_simd16;
449 grf_start2 = wm_prog_data->dispatch_grf_start_reg_16;
450 }
451 } else if (pipeline->ps_simd16 != NO_KERNEL) {
452 ksp0 = pipeline->ps_simd16;
453 grf_start0 = wm_prog_data->dispatch_grf_start_reg_16;
454 } else {
455 unreachable("no ps shader");
456 }
457
458 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PS,
459 .KernelStartPointer0 = ksp0,
460
461 .SingleProgramFlow = false,
462 .VectorMaskEnable = true,
463 .SamplerCount = 1,
464
465 .ScratchSpaceBasePointer = 0,
466 .PerThreadScratchSpace = 0,
467
468 .MaximumNumberofThreadsPerPSD = 64 - 2,
469 .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
470 POSOFFSET_SAMPLE: POSOFFSET_NONE,
471 .PushConstantEnable = wm_prog_data->base.nr_params > 0,
472 ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
473 ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
474 ._32PixelDispatchEnable = false,
475
476 .DispatchGRFStartRegisterForConstantSetupData0 = grf_start0,
477 .DispatchGRFStartRegisterForConstantSetupData1 = 0,
478 .DispatchGRFStartRegisterForConstantSetupData2 = grf_start2,
479
480 .KernelStartPointer1 = 0,
481 .KernelStartPointer2 = ksp2);
482
483 bool per_sample_ps = false;
484 anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PS_EXTRA,
485 .PixelShaderValid = true,
486 .PixelShaderKillsPixel = wm_prog_data->uses_kill,
487 .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
488 .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
489 .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
490 .PixelShaderIsPerSample = per_sample_ps);
491
492 *pPipeline = (VkPipeline) pipeline;
493
494 return VK_SUCCESS;
495
496 fail:
497 anv_device_free(device, pipeline);
498
499 return result;
500 }
501
502 VkResult
503 anv_pipeline_destroy(struct anv_pipeline *pipeline)
504 {
505 anv_compiler_free(pipeline);
506 anv_batch_finish(&pipeline->batch, pipeline->device);
507 anv_device_free(pipeline->device, pipeline);
508
509 return VK_SUCCESS;
510 }
511
512 VkResult anv_CreateGraphicsPipelineDerivative(
513 VkDevice device,
514 const VkGraphicsPipelineCreateInfo* pCreateInfo,
515 VkPipeline basePipeline,
516 VkPipeline* pPipeline)
517 {
518 stub_return(VK_UNSUPPORTED);
519 }
520
521 VkResult anv_CreateComputePipeline(
522 VkDevice device,
523 const VkComputePipelineCreateInfo* pCreateInfo,
524 VkPipeline* pPipeline)
525 {
526 stub_return(VK_UNSUPPORTED);
527 }
528
529 VkResult anv_StorePipeline(
530 VkDevice device,
531 VkPipeline pipeline,
532 size_t* pDataSize,
533 void* pData)
534 {
535 stub_return(VK_UNSUPPORTED);
536 }
537
538 VkResult anv_LoadPipeline(
539 VkDevice device,
540 size_t dataSize,
541 const void* pData,
542 VkPipeline* pPipeline)
543 {
544 stub_return(VK_UNSUPPORTED);
545 }
546
547 VkResult anv_LoadPipelineDerivative(
548 VkDevice device,
549 size_t dataSize,
550 const void* pData,
551 VkPipeline basePipeline,
552 VkPipeline* pPipeline)
553 {
554 stub_return(VK_UNSUPPORTED);
555 }
556
557 // Pipeline layout functions
558
559 VkResult anv_CreatePipelineLayout(
560 VkDevice _device,
561 const VkPipelineLayoutCreateInfo* pCreateInfo,
562 VkPipelineLayout* pPipelineLayout)
563 {
564 struct anv_device *device = (struct anv_device *) _device;
565 struct anv_pipeline_layout *layout;
566
567 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO);
568
569 layout = anv_device_alloc(device, sizeof(*layout), 8,
570 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
571 if (layout == NULL)
572 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
573
574 layout->num_sets = pCreateInfo->descriptorSetCount;
575
576 uint32_t surface_start[VK_NUM_SHADER_STAGE] = { 0, };
577 uint32_t sampler_start[VK_NUM_SHADER_STAGE] = { 0, };
578
579 for (uint32_t s = 0; s < VK_NUM_SHADER_STAGE; s++) {
580 layout->stage[s].surface_count = 0;
581 layout->stage[s].sampler_count = 0;
582 }
583
584 for (uint32_t i = 0; i < pCreateInfo->descriptorSetCount; i++) {
585 struct anv_descriptor_set_layout *set_layout =
586 (struct anv_descriptor_set_layout *) pCreateInfo->pSetLayouts[i];
587
588 layout->set[i].layout = set_layout;
589 for (uint32_t s = 0; s < VK_NUM_SHADER_STAGE; s++) {
590 layout->set[i].surface_start[s] = surface_start[s];
591 surface_start[s] += set_layout->stage[s].surface_count;
592 layout->set[i].sampler_start[s] = sampler_start[s];
593 sampler_start[s] += set_layout->stage[s].sampler_count;
594
595 layout->stage[s].surface_count += set_layout->stage[s].surface_count;
596 layout->stage[s].sampler_count += set_layout->stage[s].sampler_count;
597 }
598 }
599
600 *pPipelineLayout = (VkPipelineLayout) layout;
601
602 return VK_SUCCESS;
603 }