svp64-primer/summary.tex

   1 \section{Summary}
   2 Simple-V is a Scalable Vector Specification for a hardware for-loop that
   3 ONLY uses scalar instructions.
   4
   5 \begin{itemize}
   6 \item The Power ISA v3.1 Specification is not altered in any way.
   7   v3.1 Code-compatibility is guaranteed.
   8 \item Does not require sacrificing 32-bit Major Opcodes.
   9 \item Does not require adding duplicates of instructions
  10       (popcnt, popcntw, popcntd, vpopcntb, vpopcnth, vpopcntw, vpopcntd)
  11 \item Specifically designed to be easily implemented
  12   on top of an existing Micro-architecture (especially
  13   Superscalar Out-of-Order Multi-issue) without
  14   disruptive full architectural redesigns.
  15 \item Divided into Compliancy Levels to suit differing needs.
  16 \item At the highest Compliancy Level only requires five instructions
  17   (SVE2 requires appx 9,000. AVX-512 around 10,000. RVV around
  18   300).
  19 \item Predication, an often-requested feature, is added cleanly
  20   (without modifying the v3.1 Power ISA)
  21 \item In-registers arbitrary-sized Matrix Multiply is achieved in three
  22   instructions (without adding any v3.1 Power ISA instructions)
  23 \item Full DCT and FFT RADIX2 Triple-loops are achieved with dramatically
  24   reduced instruction count, and power consumption expected to greatly
  25   reduce. Normally found only in high-end VLIW DSPs (TI MSP, Qualcomm
  26   Hexagon)
  27 \item Fail-First Load/Store allows strncpy to be implemented in around 14
  28   instructions (hand-optimised VSX assembler is 240).
  29 \item Inner loop of MP3 implemented in under 100 instructions
  30   (gcc produces 450 for the same function)
  31 \end{itemize}
  32
  33 All areas investigated so far consistently showed reductions in executable
  34 size, which as outlined in \cite{SIMD_HARM} has an indirect reduction in
  35 power consumption due to less I-Cache/TLB pressure and also Issue remaining
  36 idle for long periods.
  37
  38 Simple-V has been specifically and carefully crafted to respect
  39 the Power ISA's Supercomputing pedigree.
  40
  41 \pagebreak
  42
  43 \subsection{What is SIMD?}
  44
  45 \ac{SIMD} is a way of partitioning existing \ac{CPU}
  46 registers of 64-bit length into smaller 8-, 16-, 32-bit pieces
  47 \cite{SIMD_HARM}\cite{SIMD_HPC}. These partitions can then be operated
  48 on simultaneously, and the initial values and results being stored as
  49 entire 64-bit registers. The SIMD instruction opcode includes the data
  50 width and the operation to perform.
  51 \par
  52
  53 \begin{figure}[hb]
  54     \centering
  55         \includegraphics[width=0.6\linewidth]{simd_axb}
  56         \caption{SIMD multiplication}
  57         \label{fig:simd_axb}
  58 \end{figure}
  59
  60 This method can have a huge advantage for rapid processing of
  61 vector-type data (image/video, physics simulations, cryptography,
  62 etc.)\cite{SIMD_WASM}, and thus on paper is very attractive compared to
  63 scalar-only instructions.
  64 \textit{As long as the data width fits the workload, everything is fine}.
  65 \par
  66
  67 SIMD registers are of a fixed length and thus to achieve greater
  68 performance, CPU architects typically increase the width of registers
  69 (to 128-, 256-, 512-bit etc) for more partitions.\par Additionally,
  70 binary compatibility is an important feature, and thus each doubling
  71 of SIMD registers also expands the instruction set. The number of
  72 instructions quickly balloons and this can be seen in popular \ac{ISA},
  73 for example IA-32 expanding from 80 to about 1400 instructions since
  74 1978\cite{SIMD_HARM}.\par
  75
  76 \subsection{Vector Architectures}
  77 An older alternative exists to utilise data parallelism - vector
  78 architectures. Vector CPUs collect operands from the main memory, and
  79 store them in large, sequential vector registers.\par
  80
  81 \begin{figure}[hb]
  82     \centering
  83         \includegraphics[width=0.6\linewidth]{cray_vector_regs}
  84         \caption{Cray Vector registers: 8 registers, 64 elements each}
  85         \label{fig:cray_vector_regs}
  86 \end{figure}
  87
  88 A simple vector processor might operate on one element at a time,
  89 however as the element operations are usually independent,
  90 a processor could be made to compute all of the vector's
  91 elements simultaneously, taking advantage of multiple pipelines.\par
  92
  93 Typically, today's vector processors can execute two, four, or eight
  94 64-bit elements per clock cycle\cite{SIMD_HARM}. Such processors can also
  95 deal with (in hardware) fringe cases where the vector length is not a
  96 multiple of the number of elements. The element data width is variable
  97 (just like in SIMD) but it is the \textit{number} of elements being
  98 variable under control of a "setvl" instruction that makes Vector ISAs
  99 "Scalable"
 100 \par
 101
 102 RISC-V Vector extension (RVV) supports a VL of up to $2^{16}$ or $65536$ bits,
 103 which can fit 1024 64-bit words \cite{riscv-v-spec}.  The Cray-1 had
 104 8 Vector Registers with up to 64 elements.  An early Draft of RVV supported
 105 overlaying the Vector Registers onto the Floating Point registers, similar
 106 to x86 "MMX".
 107
 108 Simple-V's "Vector" Registers are specifically designed to fit on top of
 109 the Scalar (GPR, FPR) register files, which are extended from the default
 110 of 32, to 128 entries in the Libre-SOC implementation.  This is a primary
 111 reason why Simple-V can be added on top of an existing Scalar ISA, and
 112 \textit{in particular} why there is no need to add Vector Registers or
 113 Vector instructions.
 114
 115 \begin{figure}[hb]
 116     \centering
 117         \includegraphics[width=0.6\linewidth]{svp64_regs}
 118         \caption{three instructions, same vector length, different element widths}
 119         \label{fig:svp64_regs}
 120 \end{figure}
 121
 122 \subsection{Comparison Between SIMD and Vector}
 123 \textit{(Need to add more here, use example from \cite{SIMD_HARM}?)}
 124
 125 \subsubsection{Code Example}
 126 \begin{verbatim}
 127 test test
 128 \end{verbatim}
 129
 130 \subsection{Shortfalls of SIMD}
 131 Five digit Opcode proliferation (10,000 instructions) is overwhelming.
 132 The following are just some of the reasons why SIMD is unsustainable as
 133 the number of instructions increase:
 134 \begin{itemize}
 135         \item Hardware design, ASIC routing etc.
 136         \item Compiler design
 137         \item Documentation of the ISA
 138         \item Manual coding and optimisation
 139         \item Time to support the platform
 140         \item Compilance Suite development and testing
 141     \item Protracted Variable-Length encoding (x86) severely compromises
 142           Multi-issue decoding
 143 \end{itemize}
 144
 145 \subsection{Simple Vectorisation}
 146 \ac{SV} is a Scalable Vector ISA designed for hybrid workloads (CPU, GPU,
 147 VPU, 3D?).  Includes features normally found only on Cray-style Supercomputers
 148 (Cray-1, NEC SX-Aurora) and GPUs.  Keeps to a strict uniform RISC paradigm,
 149 leveraging a scalar ISA by using "Prefixing".
 150 \textbf{No dedicated vector opcodes exist in SV, at all}.
 151
 152 \vspace{10pt}
 153 Main design principles
 154 \begin{itemize}
 155         \item Introduce by implementing on top of existing Power ISA
 156         \item Effectively a \textbf{hardware for-loop}, pauses main PC,
 157               issues multiple scalar operations
 158         \item Preserves underlying scalar execution dependencies as if
 159               the for-loop had been expanded into actual scalar instructions
 160         ("preserving Program Order")
 161         \item Augments existing instructions by adding "tags" - provides
 162           Vectorisation "context" rather than adding new opcodes.
 163         \item Does not modify or deviate from the underlying scalar
 164           Power ISA unless there's a significant performance boost or other
 165           advantage in the vector space
 166         \item Aimed at Supercomputing: avoids creating significant
 167               \textit{sequential dependency hazards}, allowing \textbf{high
 168               performance multi-issue superscalar microarchitectures} to be
 169           leveraged.
 170 \end{itemize}
 171
 172 Advantages include:
 173 \begin{itemize}
 174         \item Easy to create first (and sometimes only) implementation
 175               as a literal for-loop in hardware, simulators, and compilers.
 176         \item Hardware Architects may understand and implement SV as
 177           being an extra pipeline stage, inserted between decode and
 178           issue. Essentially a simple for-loop issuing element-level
 179           sub-instructions.
 180         \item More complex HDL can be done by repeating existing scalar
 181               ALUs and pipelines as blocks, leveraging existing Multi-Issue
 182           Infrastructure.
 183         \item Mostly high-level "context" which does not significantly
 184           deviate from scalar Power ISA and, in its purest form
 185           being a "for-loop around scalar instructions". Thus SV is
 186           minimally-disruptive and consequently has a reasonable chance
 187           of broad community adoption and acceptance.
 188         \item Obliterates SIMD opcode proliferation
 189           ($O(N^6)$) as well as dedicated Vectorisation
 190           ISAs. No more separate vector instructions.
 191 \end{itemize}
 192
 193 \subsubsection{Prefix 64 - SVP64}
 194
 195 SVP64, is a specification designed to solve the problems caused by
 196 SIMD implementations by:
 197 \begin{itemize}
 198         \item Simplifying the hardware design
 199         \item Reducing maintenance overhead
 200         \item Reducing code size and power consumption
 201         \item Easier for compilers, coders, documentation
 202         \item Time to support platform is a fraction of conventional SIMD
 203               (Less money on R\&D, faster to deliver)
 204 \end{itemize}
 205
 206 - Intel SIMD has been incrementally added to for decades, requires backwards
 207   interoperability, and thus has a greater complexity (?)
 208
 209
 210 - What are we going to gain?
 211
 212 -for loop, increment registers RT, RA, RB
 213 -few instructions, easier to implement and maintain
 214 -example assembly code
 215 -ARM has already started to add to libC SVE2 support
 216
 217 1970 x86 comparison