1 -- syscon module, a bunch of misc global system control MMIO registers
3 use ieee.std_logic_1164.all;
4 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001";
17 DRAM_INIT_SIZE : integer;
18 HAS_SPI_FLASH : boolean;
19 SPI_FLASH_OFFSET : integer;
20 HAS_LITEETH : boolean;
21 UART0_IS_16550 : boolean;
29 wishbone_in : in wb_io_master_out;
30 wishbone_out : out wb_io_slave_out;
32 -- System control ports
33 dram_at_0 : out std_ulogic;
34 core_reset : out std_ulogic;
35 soc_reset : out std_ulogic
40 architecture behaviour of syscon is
41 -- Register address bits
42 constant SYS_REG_BITS : positive := 6;
44 -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg)
45 constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000000";
46 constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000001";
47 constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000010";
48 constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000011";
49 constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000100";
50 constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000101";
51 constant SYS_REG_DRAMINITINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000110";
52 constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000111";
53 constant SYS_REG_UART0_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001000";
54 constant SYS_REG_UART1_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001001";
56 -- Muxed reg read signal
57 signal reg_out : std_ulogic_vector(63 downto 0);
60 constant SYS_REG_INFO_HAS_UART : integer := 0; -- Has a UART (always set)
61 constant SYS_REG_INFO_HAS_DRAM : integer := 1; -- Has DRAM
62 constant SYS_REG_INFO_HAS_BRAM : integer := 2; -- Has "main" BRAM
63 constant SYS_REG_INFO_HAS_SPIF : integer := 3; -- Has SPI flash
64 constant SYS_REG_INFO_HAS_LETH : integer := 4; -- Has LiteEth ethernet
65 constant SYS_REG_INFO_HAS_LSYS : integer := 5; -- Has 6-bit address syscon
66 constant SYS_REG_INFO_HAS_URT1 : integer := 6; -- Has second UART
67 constant SYS_REG_INFO_HAS_ARTB : integer := 7; -- Has architected TB frequency
69 -- BRAMINFO contains the BRAM size in the bottom 52 bits
70 -- DRAMINFO contains the DRAM size if any in the bottom 52 bits
71 -- (both have reserved top bits for future use)
72 -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits
75 constant SYS_REG_CTRL_BITS : positive := 3;
76 constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0;
77 constant SYS_REG_CTRL_CORE_RESET : integer := 1;
78 constant SYS_REG_CTRL_SOC_RESET : integer := 2;
80 -- SPI Info register bits
82 -- Top 32-bit is flash offset which is the amount of flash
83 -- reserved for the FPGA bitfile if any
84 constant SYS_REG_SPI_INFO_IS_FLASH : integer := 0;
86 -- UART0/1 info registers bits
88 -- 0 ..31 : UART clock freq (in HZ)
89 -- 32 : UART is 16550 (otherwise pp)
93 signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
94 signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
97 signal reg_info : std_ulogic_vector(63 downto 0);
98 signal reg_braminfo : std_ulogic_vector(63 downto 0);
99 signal reg_draminfo : std_ulogic_vector(63 downto 0);
100 signal reg_dramiinfo : std_ulogic_vector(63 downto 0);
101 signal reg_clkinfo : std_ulogic_vector(63 downto 0);
102 signal reg_spiinfo : std_ulogic_vector(63 downto 0);
103 signal reg_uart0info : std_ulogic_vector(63 downto 0);
104 signal reg_uart1info : std_ulogic_vector(63 downto 0);
105 signal info_has_dram : std_ulogic;
106 signal info_has_bram : std_ulogic;
107 signal info_has_uart : std_ulogic;
108 signal info_has_spif : std_ulogic;
109 signal info_has_leth : std_ulogic;
110 signal info_has_urt1 : std_ulogic;
111 signal info_clk : std_ulogic_vector(39 downto 0);
112 signal info_fl_off : std_ulogic_vector(31 downto 0);
113 signal uinfo_16550 : std_ulogic;
114 signal uinfo_freq : std_ulogic_vector(31 downto 0);
116 -- Wishbone response latch
117 signal wb_rsp : wb_io_slave_out;
120 -- Generated output signals
121 dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
122 soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
123 core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
125 -- Info register is hard wired
126 info_has_uart <= '1' when HAS_UART else '0';
127 info_has_dram <= '1' when HAS_DRAM else '0';
128 info_has_bram <= '1' when BRAM_SIZE /= 0 else '0';
129 info_has_spif <= '1' when HAS_SPI_FLASH else '0';
130 info_has_leth <= '1' when HAS_LITEETH else '0';
131 info_has_urt1 <= '1' when HAS_UART1 else '0';
132 info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40));
133 reg_info <= (SYS_REG_INFO_HAS_UART => info_has_uart,
134 SYS_REG_INFO_HAS_DRAM => info_has_dram,
135 SYS_REG_INFO_HAS_BRAM => info_has_bram,
136 SYS_REG_INFO_HAS_SPIF => info_has_spif,
137 SYS_REG_INFO_HAS_LETH => info_has_leth,
138 SYS_REG_INFO_HAS_LSYS => '1',
139 SYS_REG_INFO_HAS_URT1 => info_has_urt1,
142 reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
143 reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
144 else (others => '0');
145 reg_dramiinfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_INIT_SIZE, 52)) when HAS_DRAM
146 else (others => '0');
147 reg_clkinfo <= (39 downto 0 => info_clk,
149 info_fl_off <= std_ulogic_vector(to_unsigned(SPI_FLASH_OFFSET, 32));
150 reg_spiinfo <= (31 downto 0 => info_fl_off,
153 -- Control register read composition
154 reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0',
155 SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl);
157 -- UART info registers read composition
158 uinfo_16550 <= '1' when UART0_IS_16550 else '0';
159 uinfo_freq <= std_ulogic_vector(to_unsigned(CLK_FREQ, 32));
160 reg_uart0info <= (32 => uinfo_16550,
161 31 downto 0 => uinfo_freq,
163 reg_uart1info <= (32 => '1',
164 31 downto 0 => uinfo_freq,
168 wb_rsp.ack <= wishbone_in.cyc and wishbone_in.stb;
169 with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select reg_out <=
170 SIG_VALUE when SYS_REG_SIG,
171 reg_info when SYS_REG_INFO,
172 reg_braminfo when SYS_REG_BRAMINFO,
173 reg_draminfo when SYS_REG_DRAMINFO,
174 reg_dramiinfo when SYS_REG_DRAMINITINFO,
175 reg_clkinfo when SYS_REG_CLKINFO,
176 reg_ctrl_out when SYS_REG_CTRL,
177 reg_spiinfo when SYS_REG_SPIFLASHINFO,
178 reg_uart0info when SYS_REG_UART0_INFO,
179 reg_uart1info when SYS_REG_UART1_INFO,
180 (others => '0') when others;
181 wb_rsp.dat <= reg_out(63 downto 32) when wishbone_in.adr(2) = '1' else
182 reg_out(31 downto 0);
185 -- Wishbone response latch
186 regs_read: process(clk)
188 if rising_edge(clk) then
189 -- Send response from latch
190 wishbone_out <= wb_rsp;
195 regs_write: process(clk)
197 if rising_edge(clk) then
199 reg_ctrl <= (others => '0');
201 if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
202 -- Change this if CTRL ever has more than 32 bits
203 if wishbone_in.adr(SYS_REG_BITS+2 downto 3) = SYS_REG_CTRL and
204 wishbone_in.adr(2) = '0' then
205 reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <=
206 wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0);
211 if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then
212 reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0';
214 if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then
215 reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0';
218 -- If BRAM doesn't exist, force DRAM at 0
219 if BRAM_SIZE = 0 then
220 reg_ctrl(SYS_REG_CTRL_DRAM_AT_0) <= '1';
226 end architecture behaviour;