system/alpha/h/rpb.h

   1 /*
   2  * Copyright 1990 Hewlett-Packard Development Company, L.P.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 /* $NetBSD: rpb.h,v 1.20 1998/04/15 00:47:33 mjacob Exp $ */
  26 /* $FreeBSD: src/sys/alpha/include/rpb.h,v 1.9 2001/03/30 22:04:08 gallatin Exp $ */
  27
  28 /*
  29  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
  30  * All rights reserved.
  31  *
  32  * Author: Keith Bostic, Chris G. Demetriou
  33  *
  34  * Permission to use, copy, modify and distribute this software and
  35  * its documentation is hereby granted, provided that both the copyright
  36  * notice and this permission notice appear in all copies of the
  37  * software, derivative works or modified versions, and any portions
  38  * thereof, and that both notices appear in supporting documentation.
  39  *
  40  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  41  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  42  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  43  *
  44  * Carnegie Mellon requests users of this software to return to
  45  *
  46  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  47  *  School of Computer Science
  48  *  Carnegie Mellon University
  49  *  Pittsburgh PA 15213-3890
  50  *
  51  * any improvements or extensions that they make and grant Carnegie the
  52  * rights to redistribute these changes.
  53  */
  54
  55 /*
  56  * Defines for the architected startup addresses.
  57  */
  58 #define HWRPB_ADDR      0x10000000      /* 256 MB */
  59 #define BOOT_ADDR       0x20000000      /* 512 MB */
  60 #define PGTBL_ADDR      0x40000000      /*   1 GB */
  61
  62 /*
  63  * Values for the "haltcode" field in the per-cpu portion of the HWRPB
  64  *
  65  * Bit defines for the "sysvar" field in the HWRPB.
  66  * Each platform has different values for SYSBOARD and IOBOARD bits.
  67  */
  68 #define HALT_PWRUP      0               /* power up */
  69 #define HALT_OPR        1               /* operator issued halt cmd */
  70 #define HALT_KSTK       2               /* kernel stack not valid */
  71 #define HALT_SCBB       3               /* invalid SCBB */
  72 #define HALT_PTBR       4               /* invalid PTBR */
  73 #define HALT_EXE        5               /* kernel executed halt instruction */
  74 #define HALT_DBLE       6               /* double error abort */
  75
  76 /*
  77  * Bit defines for the "state" field in the per-cpu portion of the HWRPB
  78  */
  79 #define STATE_BIP       0x00000001      /* bootstrap in progress */
  80 #define STATE_RC        0x00000002      /* restart capable */
  81 #define STATE_PA        0x00000004      /* processor available to OS */
  82 #define STATE_PP        0x00000008      /* processor present */
  83 #define STATE_OH        0x00000010      /* operator halted */
  84 #define STATE_CV        0x00000020      /* context valid */
  85 #define STATE_PV        0x00000040      /* PALcode valid */
  86 #define STATE_PMV       0x00000080      /* PALcode memory valid */
  87 #define STATE_PL        0x00000100      /* PALcode loaded */
  88 #define STATE_HALT_MASK 0x00ff0000      /* Mask for Halt Requested field */
  89 #define STATE_DEFAULT   0x00000000      /* Default (no specific action) */
  90 #define STATE_SVRS_TERM 0x00010000      /* SAVE_TERM/RESTORE_TERM Exit */
  91 #define STATE_COLD_BOOT 0x00020000      /* Cold Bootstrap Requested */
  92 #define STATE_WARM_BOOT 0x00030000      /* Warm Bootstrap Requested */
  93 #define STATE_HALT      0x00040000      /* Remain halted (no restart) */
  94
  95
  96 #define SV_PF_RSVD      0x00000000      /* RESERVED */
  97 #define SV_RESERVED     0x00000000      /* All STS bits; 0 for back compat */
  98 #define SV_MPCAP        0x00000001      /* MP capable */
  99 #define SV_PF_UNITED    0x00000020      /* United */
 100 #define SV_PF_SEPARATE  0x00000040      /* Separate */
 101 #define SV_PF_FULLBB    0x00000060      /* Full battery backup */
 102 #define SV_POWERFAIL    0x000000e0      /* Powerfail implementation */
 103 #define SV_PF_RESTART   0x00000100      /* Powerfail restart */
 104
 105 #define SV_GRAPHICS     0x00000200      /* Embedded graphics processor */
 106
 107 #define SV_STS_MASK     0x0000fc00      /* STS bits - system and I/O board */
 108 #define SV_SANDPIPER    0x00000400      /* others define system platforms */
 109 #define SV_FLAMINGO     0x00000800      /* STS BIT SETTINGS */
 110 #define SV_HOTPINK      0x00000c00      /* STS BIT SETTINGS */
 111 #define SV_FLAMINGOPLUS 0x00001000      /* STS BIT SETTINGS */
 112 #define SV_ULTRA        0x00001400      /* STS BIT SETTINGS */
 113 #define SV_SANDPLUS     0x00001800      /* STS BIT SETTINGS */
 114 #define SV_SANDPIPER45  0x00001c00      /* STS BIT SETTINGS */
 115 #define SV_FLAMINGO45   0x00002000      /* STS BIT SETTINGS */
 116
 117 #define SV_SABLE        0x00000400      /* STS BIT SETTINGS */
 118
 119 #define SV_KN20AA       0x00000400      /* STS BIT SETTINGS */
 120
 121 /*
 122  * Values for the "console type" field in the CTB portion of the HWRPB
 123  */
 124 #define CONS_NONE       0               /* no console present */
 125 #define CONS_SRVC       1               /* console is service processor */
 126 #define CONS_DZ         2               /* console is dz/dl VT device */
 127 #define CONS_GRPH       3               /* cons is gfx dev w/ dz/dl keybd*/
 128 #define CONS_REM        4               /* cons is remote, protocal enet/MOP */
 129
 130 /*
 131  * PALcode variants that we're interested in.
 132  * Used as indices into the "palrev_avail" array in the per-cpu portion
 133  * of the HWRPB.
 134  */
 135 #define PALvar_reserved 0
 136 #define PALvar_OpenVMS  1
 137 #define PALvar_OSF1     2
 138
 139 /*
 140  * The Alpha restart parameter block, which is a page or 2 in low memory
 141  */
 142 struct rpb {
 143     struct rpb *rpb_selfref;    /* 000: physical self-reference */
 144     long  rpb_string;           /* 008: contains string "HWRPB" */
 145     long  rpb_vers;             /* 010: HWRPB version number */
 146     ulong rpb_size;             /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
 147     ulong rpb_cpuid;            /* 020: primary cpu id */
 148     ulong rpb_pagesize;         /* 028: page size in bytes */
 149     ulong rpb_addrbits;         /* 030: number of phys addr bits */
 150     ulong rpb_maxasn;           /* 038: max valid ASN */
 151     char  rpb_ssn[16];          /* 040: system serial num: 10 ascii chars */
 152     ulong grpb_systype;         /* 050: system type */
 153     long  rpb_sysvar;           /* 058: system variation */
 154     long  rpb_sysrev;           /* 060: system revision */
 155     ulong rpb_clock;            /* 068: scaled interval clock intr freq */
 156     ulong rpb_counter;          /* 070: cycle counter frequency */
 157     ulong rpb_vptb;             /* 078: virtual page table base */
 158     long  rpb_res1;             /* 080: reserved */
 159     ulong rpb_trans_off;        /* 088: offset to translation buffer hint */
 160     ulong rpb_numprocs;         /* 090: number of processor slots */
 161     ulong rpb_slotsize;         /* 098: per-cpu slot size */
 162     ulong rpb_percpu_off;       /* 0A0: offset to per_cpu slots */
 163     ulong rpb_num_ctb;          /* 0A8: number of CTBs */
 164     ulong rpb_ctb_size;         /* 0B0: bytes in largest CTB */
 165     ulong rpb_ctb_off;          /* 0B8: offset to CTB (cons term block) */
 166     ulong rpb_crb_off;          /* 0C0: offset to CRB (cons routine block) */
 167     ulong rpb_mdt_off;          /* 0C8: offset to memory descriptor table */
 168     ulong rpb_config_off;       /* 0D0: offset to config data block */
 169     ulong rpb_fru_off;          /* 0D8: offset to FRU table */
 170     void  (*rpb_saveterm)();    /* 0E0: virt addr of save term routine */
 171     long  rpb_saveterm_pv;      /* 0E8: proc value for save term routine */
 172     void  (*rpb_rstrterm)();    /* 0F0: virt addr of restore term routine */
 173     long  rpb_rstrterm_pv;      /* 0F8: proc value for restore term routine */
 174     void  (*rpb_restart)();     /* 100: virt addr of CPU restart routine */
 175     long  rpb_restart_pv;       /* 108: proc value for CPU restart routine */
 176     long  rpb_software;         /* 110: used to determine presence of kdebug */
 177     long  rpb_hardware;         /* 118: reserved for hardware */
 178     long  rpb_checksum;         /* 120: checksum of prior entries in rpb */
 179     long  rpb_rxrdy;            /* 128: receive ready bitmask */
 180     long  rpb_txrdy;            /* 130: transmit ready bitmask */
 181     ulong rpb_dsr_off;          /* 138: Dynamic System Recog. offset */
 182 };
 183
 184 #define rpb_kdebug rpb_software
 185
 186 #define OSF_HWRPB_ADDR  ((vm_offset_t)(-1L << 23))
 187
 188 /*
 189  * This is the format for the boot/restart HWPCB.  It must match the
 190  * initial fields of the pcb structure as defined in pcb.h, but must
 191  * additionally contain the appropriate amount of padding to line up
 192  * with formats used by other palcode types.
 193  */
 194 struct bootpcb {
 195     long rpb_ksp;               /* 000: kernel stack pointer */
 196     long rpb_usp;               /* 008: user stack pointer */
 197     long rpb_ptbr;              /* 010: page table base register */
 198     int  rpb_cc;                /* 018: cycle counter */
 199     int  rpb_asn;               /* 01C: address space number */
 200     long rpb_proc_uniq;         /* 020: proc/thread unique value */
 201     long rpb_fen;               /* 028: floating point enable */
 202     long rpb_palscr[2];         /* 030: pal scratch area */
 203     long rpb_pcbpad[8];         /* 040: padding for fixed size */
 204 };
 205
 206 /*
 207  * Inter-Console Communications Buffer
 208  * Used for the primary processor to communcate with the console
 209  * of secondary processors.
 210  */
 211 struct iccb {
 212     uint iccb_rxlen;            /* receive length in bytes      */
 213     uint iccb_txlen;            /* transmit length in bytes     */
 214     char iccb_rxbuf[80];        /* receive buffer               */
 215     char iccb_txbuf[80];        /* transmit buffer              */
 216 };
 217
 218 /*
 219  * The per-cpu portion of the Alpha HWRPB.
 220  * Note that the main portion of the HWRPB is of variable size,
 221  * hence this must be a separate structure.
 222  *
 223  */
 224 struct rpb_percpu {
 225     struct bootpcb rpb_pcb;     /* 000: boot/restart HWPCB */
 226     long rpb_state;             /* 080: per-cpu state bits */
 227     long rpb_palmem;            /* 088: palcode memory length */
 228     long rpb_palscratch;        /* 090: palcode scratch length */
 229     long rpb_palmem_addr;       /* 098: phys addr of palcode mem space */
 230     long rpb_palscratch_addr;   /* 0A0: phys addr of palcode scratch space */
 231     long rpb_palrev;            /* 0A8: PALcode rev required */
 232     long rpb_proctype;          /* 0B0: processor type */
 233     long rpb_procvar;           /* 0B8: processor variation */
 234     long rpb_procrev;           /* 0C0: processor revision */
 235     char rpb_procsn[16];        /* 0C8: proc serial num: 10 ascii chars */
 236     long rpb_logout;            /* 0D8: phys addr of logout area */
 237     long rpb_logout_len;        /* 0E0: length in bytes of logout area */
 238     long rpb_haltpb;            /* 0E8: halt pcb base */
 239     long rpb_haltpc;            /* 0F0: halt pc */
 240     long rpb_haltps;            /* 0F8: halt ps */
 241     long rpb_haltal;            /* 100: halt arg list (R25) */
 242     long rpb_haltra;            /* 108: halt return address (R26) */
 243     long rpb_haltpv;            /* 110: halt procedure value (R27) */
 244     long rpb_haltcode;          /* 118: reason for halt */
 245     long rpb_software;          /* 120: for software */
 246     struct iccb rpb_iccb;       /* 128: inter-console communications buffer */
 247     long rpb_palrev_avail[16];  /* 1D0: PALcode revs available */
 248     long rpb_pcrsvd[6];         /* 250: reserved for arch use */
 249 /* the dump stack grows from the end of the rpb page not to reach here */
 250 };
 251
 252 /* The firmware revision is in the (unused) first entry of palrevs available */
 253 #define rpb_firmrev rpb_palrev_avail[0]
 254
 255 /*
 256  * The memory cluster descriptor.
 257  */
 258 struct rpb_cluster {
 259     long rpb_pfn;               /* 000: starting PFN of this cluster */
 260     long rpb_pfncount;          /* 008: count of PFNs in this cluster */
 261     long rpb_pfntested;         /* 010: count of tested PFNs in cluster */
 262     long rpb_va;                /* 018: va of bitmap */
 263     long rpb_pa;                /* 020: pa of bitmap */
 264     long rpb_checksum;          /* 028: checksum of bitmap */
 265     long rpb_usage;             /* 030: usage of cluster */
 266 };
 267 #define CLUSTER_USAGE_OS        ((long)0)
 268 #define CLUSTER_USAGE_PAL       ((long)1)
 269 #define CLUSTER_USAGE_NVRAM     ((long)2)
 270
 271 /*
 272  * The "memory descriptor table" portion of the HWRPB.
 273  * Note that the main portion of the HWRPB is of variable size and there is a
 274  * variable number of per-cpu slots, hence this must be a separate structure.
 275  * Also note that the memory descriptor table contains a fixed portion plus
 276  * a variable number of "memory cluster descriptors" (one for each "cluster"
 277  * of memory).
 278  */
 279 struct rpb_mdt {
 280     long rpb_checksum;          /* 000: checksum of entire mem desc table */
 281     long rpb_impaddr;           /* 008: PA of implementation dep info */
 282     long rpb_numcl;             /* 010: number of clusters */
 283     struct rpb_cluster rpb_cluster[1];  /* first instance of a cluster */
 284 };
 285
 286 /*
 287  * The "Console Terminal Block" portion of the HWRPB, for serial line
 288  * UART console device.
 289  */
 290 struct ctb_tt {
 291
 292     long ctb_type;               /*   0: always 4 */
 293     long ctb_unit;               /*   8: */
 294     long ctb_reserved;           /*  16: */
 295     long ctb_len;                /*  24: bytes of info */
 296     long ctb_ipl;                /*  32: console ipl level */
 297     long ctb_tintr_vec;          /*  40: transmit vec (0x800) */
 298     long ctb_rintr_vec;          /*  48: receive vec (0x800) */
 299 #define CTB_GRAPHICS       3     /* graphics device */
 300 #define CTB_NETWORK     0xC0     /* network device */
 301 #define CTB_PRINTERPORT    2     /* printer port on the SCC */
 302     long ctb_term_type;          /*  56: terminal type */
 303     long ctb_keybd_type;         /*  64: keyboard nationality */
 304     long ctb_keybd_trans;        /*  72: trans. table addr */
 305     long ctb_keybd_map;          /*  80: map table addr */
 306     long ctb_keybd_state;        /*  88: keyboard flags */
 307     long ctb_keybd_last;         /*  96: last key entered */
 308     long ctb_font_us;            /* 104: US font table addr */
 309     long ctb_font_mcs;           /* 112: MCS font table addr */
 310     long ctb_font_width;         /* 120: font width, height */
 311     long ctb_font_height;        /* 128:         in pixels */
 312     long ctb_mon_width;          /* 136: monitor width, height */
 313     long ctb_mon_height;         /* 144:         in pixels */
 314     long ctb_dpi;                /* 152: monitor dots per inch */
 315     long ctb_planes;             /* 160: # of planes */
 316     long ctb_cur_width;          /* 168: cursor width, height */
 317     long ctb_cur_height;         /* 176:         in pixels */
 318     long ctb_head_cnt;           /* 184: # of heads */
 319     long ctb_opwindow;           /* 192: opwindow on screen */
 320     long ctb_head_offset;        /* 200: offset to head info */
 321     long ctb_putchar;            /* 208: output char to TURBO */
 322     long ctb_io_state;           /* 216: I/O flags */
 323     long ctb_listen_state;       /* 224: listener flags */
 324     long ctb_xaddr;              /* 232: extended info addr */
 325     long ctb_turboslot;          /* 248: TURBOchannel slot # */
 326     long ctb_server_off;         /* 256: offset to server info */
 327     long ctb_line_off;           /* 264: line parameter offset */
 328     char ctb_csd;                /* 272: console specific data */
 329 };
 330
 331 /*
 332  * The "Console Terminal Block" portion of the HWRPB.
 333  */
 334 struct rpb_ctb {
 335     long rpb_type;              /* 000: console type */
 336     long rpb_unit;              /* 008: console unit */
 337     long rpb_resv;              /* 010: reserved */
 338     long rpb_length;            /* 018: byte length of device dep portion */
 339     long rpb_first;             /* 000: first field of device dep portion */
 340 };
 341
 342 /*
 343  * The physical/virtual map for the console routine block.
 344  */
 345 struct rpb_map {
 346     long rpb_virt;              /* virtual address for map entry */
 347     long rpb_phys;              /* phys address for map entry */
 348     long rpb_pgcount;           /* page count for map entry */
 349 };
 350
 351 /*
 352  * The "Console Routine Block" portion of the HWRPB.
 353  * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
 354  */
 355 struct rpb_crb {
 356     long rpb_va_disp;           /* va of call-back dispatch rtn */
 357     long rpb_pa_disp;           /* pa of call-back dispatch rtn */
 358     long rpb_va_fixup;          /* va of call-back fixup rtn */
 359     long rpb_pa_fixup;          /* pa of call-back fixup rtn */
 360     long rpb_num;               /* number of entries in phys/virt map */
 361     long rpb_mapped_pages;      /* Number of pages to be mapped */
 362     struct rpb_map rpb_map[1];  /* first instance of a map entry */
 363 };
 364
 365 /*
 366  * These macros define where within the HWRPB the CTB and CRB are located.
 367  */
 368 #define CTB_SETUP \
 369     ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off)))
 370
 371 #define CRB_SETUP \
 372     ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off)))
 373
 374 /*
 375  * The "Dynamic System Recognition" portion of the HWRPB.
 376  * It is used to obtain the platform specific data need to allow
 377  * the platform define the platform name, the platform SMM and LURT
 378  * data for software licensing
 379  */
 380 struct rpb_dsr {
 381     long rpb_smm;               /* SMM nubber used by LMF       */
 382     ulong rpb_lurt_off;         /* offset to LURT table         */
 383     ulong rpb_sysname_off;      /* offset to sysname char count */
 384     int lurt[10];               /* XXM has one LURT entry       */
 385 };