system/alpha/palcode/ev5_impure.h

   1 #ifndef EV5_IMPURE_INCLUDED
   2 #define EV5_IMPURE_INCLUDED
   3
   4 /*
   5 // This uses the Hudson file format from "impure.h" but with the fields from
   6 // the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95
   7
   8 //orig  file:   impure.sdl
   9 //orig
  10 //orig  Abstract:       PAL impure scratch area and logout area data structure definitions for
  11 //orig          Alpha firmware.
  12 //orig
  13 //orig
  14 //orig  module  $pal_impure;
  15 //orig
  16 //orig  Edit   Date     Who       Description
  17 //orig  ---- ---------  ---  ---------------------
  18 //orig     1   7-Jul-93 JEM   Initial Entry
  19 //orig     2  18-nov-93 JEM   Add shadow bc_ctl and pmctr_ctl to impure area
  20 //orig                   Delete mvptbr
  21 //orig                   Calculate pal$logout from end of impure area
  22 //orig     3   6-dec-93 JEM   Add pmctr_ctl bitfield definitions
  23 //orig     4   3-feb-94 JEM   Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl;
  24 //orig                          add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl,
  25 //orig                              bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock
  26 //orig     5  19-feb-94 JEM   add gpr constants, and add f31,r31 back in to be consistent with ev4
  27 //orig                   add cns$ipr_offset
  28 //orig     6  18-apr-94 JEM   Add shadow bc_ctl and pmctr_ctl to impure area again.
  29 //orig     7  18-jul-94 JEM   Add bc_config shadow.   Add mchk$sys_base constant to mchk logout frame
  30 //orig
  31 //orig
  32 //orig     constant REVISION equals 7 prefix IMPURE$;            // Revision number of this file
  33 //orig
  34
  35 ** Macros for saving/restoring data to/from the PAL impure scratch
  36 ** area.
  37 **
  38 ** The console save state area is larger than the addressibility
  39 ** of the HW_LD/ST instructions (10-bit signed byte displacement),
  40 ** so some adjustments to the base offsets, as well as the offsets
  41 ** within each base region, are necessary.
  42 **
  43 ** The console save state area is divided into two segments; the
  44 ** CPU-specific segment and the platform-specific segment.  The
  45 ** state that is saved in the CPU-specific segment includes GPRs,
  46 ** FPRs, IPRs, halt code, MCHK flag, etc.  All other state is saved
  47 ** in the platform-specific segment.
  48 **
  49 ** The impure pointer will need to be adjusted by a different offset
  50 ** value for each region within a given segment.  The SAVE and RESTORE
  51 ** macros will auto-magically adjust the offsets accordingly.
  52 **
  53 */
  54
  55 #define SAVE_GPR(reg,offset,base) \
  56         stq_p   reg, ((offset-0x200)&0x3FF)(base)
  57
  58 #define RESTORE_GPR(reg,offset,base) \
  59         ldq_p   reg, ((offset-0x200)&0x3FF)(base)
  60
  61
  62 #define SAVE_FPR(reg,offset,base) \
  63         stt     reg, ((offset-0x200)&0x3FF)(base)
  64
  65 #define RESTORE_FPR(reg,offset,base) \
  66         ldt     reg, ((offset-0x200)&0x3FF)(base)
  67
  68 #define SAVE_IPR(reg,offset,base) \
  69         mfpr    v0, reg;          \
  70         stq_p   v0, ((offset-CNS_Q_IPR)&0x3FF)(base)
  71
  72 #define RESTORE_IPR(reg,offset,base) \
  73         ldq_p   v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \
  74         mtpr    v0, reg
  75
  76 #define SAVE_SHADOW(reg,offset,base) \
  77         stq_p   reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
  78
  79 #define RESTORE_SHADOW(reg,offset,base)\
  80         ldq_p   reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
  81
  82 /* orig  Structure of the processor-specific impure area */
  83
  84 /* orig aggregate impure struct prefix "" tag "";
  85  * orig         cns$flag        quadword;
  86  * orig         cns$hlt         quadword;
  87 */
  88
  89 /* Define base for debug monitor compatibility */
  90 #define CNS_Q_BASE      0x000
  91 #define CNS_Q_FLAG      0x100
  92 #define CNS_Q_HALT      0x108
  93
  94
  95 /* orig constant (
  96  * orig         cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
  97  * orig         cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
  98  * orig         cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
  99  * orig         cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
 100  * orig         ) equals . increment 8 prefix "" tag "";
 101  * orig         cns$gpr quadword dimension 32;
 102 */
 103 /* Offset to base of saved GPR area - 32 quadword */
 104 #define CNS_Q_GPR       0x110
 105 #define cns_gpr CNS_Q_GPR
 106
 107 /* orig constant (
 108  * orig         cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
 109  * orig         cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
 110  * orig         cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
 111  * orig         cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
 112  * orig         ) equals . increment 8 prefix "" tag "";
 113  * orig         cns$fpr quadword dimension 32;
 114 */
 115 /* Offset to base of saved FPR area - 32 quadwords */
 116 #define CNS_Q_FPR       0x210
 117
 118 /* orig         #t=.;
 119  * orig         cns$mchkflag quadword;
 120 */
 121 #define CNS_Q_MCHK      0x310
 122
 123 /* orig         constant cns$pt_offset equals .;
 124  * orig  constant (
 125  * orig         cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
 126  * orig         cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
 127  * orig         cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
 128  * orig         cns$pt21,cns$pt22,cns$pt23
 129  * orig         ) equals . increment 8 prefix "" tag "";
 130  * orig         cns$pt  quadword dimension 24;
 131 */
 132 /* Offset to base of saved PALtemp area - 25 quadwords */
 133 #define CNS_Q_PT        0x318
 134
 135 /* orig         cns$shadow8     quadword;
 136  * orig         cns$shadow9     quadword;
 137  * orig         cns$shadow10    quadword;
 138  * orig         cns$shadow11    quadword;
 139  * orig         cns$shadow12    quadword;
 140  * orig         cns$shadow13    quadword;
 141  * orig         cns$shadow14    quadword;
 142  * orig         cns$shadow25    quadword;
 143 */
 144 /* Offset to base of saved PALshadow area - 8 quadwords */
 145 #define CNS_Q_SHADOW    0x3D8
 146
 147 /* Offset to base of saved IPR area */
 148 #define CNS_Q_IPR       0x418
 149
 150 /* orig         constant cns$ipr_offset equals .; */
 151 /* orig         cns$exc_addr    quadword; */
 152 #define CNS_Q_EXC_ADDR          0x418
 153 /* orig         cns$pal_base    quadword; */
 154 #define CNS_Q_PAL_BASE          0x420
 155 /* orig         cns$mm_stat     quadword; */
 156 #define CNS_Q_MM_STAT           0x428
 157 /* orig         cns$va          quadword; */
 158 #define CNS_Q_VA                0x430
 159 /* orig         cns$icsr        quadword; */
 160 #define CNS_Q_ICSR              0x438
 161 /* orig         cns$ipl         quadword; */
 162 #define CNS_Q_IPL               0x440
 163 /* orig         cns$ps          quadword;       // Ibox current mode */
 164 #define CNS_Q_IPS               0x448
 165 /* orig         cns$itb_asn     quadword; */
 166 #define CNS_Q_ITB_ASN           0x450
 167 /* orig         cns$aster       quadword; */
 168 #define CNS_Q_ASTER             0x458
 169 /* orig         cns$astrr       quadword; */
 170 #define CNS_Q_ASTRR             0x460
 171 /* orig         cns$isr         quadword; */
 172 #define CNS_Q_ISR               0x468
 173 /* orig         cns$ivptbr      quadword; */
 174 #define CNS_Q_IVPTBR            0x470
 175 /* orig         cns$mcsr        quadword; */
 176 #define CNS_Q_MCSR              0x478
 177 /* orig         cns$dc_mode     quadword; */
 178 #define CNS_Q_DC_MODE           0x480
 179 /* orig         cns$maf_mode    quadword; */
 180 #define CNS_Q_MAF_MODE          0x488
 181 /* orig         cns$sirr        quadword; */
 182 #define CNS_Q_SIRR              0x490
 183 /* orig         cns$fpcsr       quadword; */
 184 #define CNS_Q_FPCSR             0x498
 185 /* orig         cns$icperr_stat quadword; */
 186 #define CNS_Q_ICPERR_STAT       0x4A0
 187 /* orig         cns$pmctr       quadword; */
 188 #define CNS_Q_PM_CTR            0x4A8
 189 /* orig         cns$exc_sum     quadword; */
 190 #define CNS_Q_EXC_SUM           0x4B0
 191 /* orig         cns$exc_mask    quadword; */
 192 #define CNS_Q_EXC_MASK          0x4B8
 193 /* orig         cns$intid       quadword; */
 194 #define CNS_Q_INT_ID            0x4C0
 195 /* orig         cns$dcperr_stat quadword; */
 196 #define CNS_Q_DCPERR_STAT       0x4C8
 197 /* orig         cns$sc_stat     quadword; */
 198 #define CNS_Q_SC_STAT           0x4D0
 199 /* orig         cns$sc_addr     quadword; */
 200 #define CNS_Q_SC_ADDR           0x4D8
 201 /* orig         cns$sc_ctl      quadword; */
 202 #define CNS_Q_SC_CTL            0x4E0
 203 /* orig         cns$bc_tag_addr quadword; */
 204 #define CNS_Q_BC_TAG_ADDR       0x4E8
 205 /* orig         cns$ei_stat     quadword; */
 206 #define CNS_Q_EI_STAT           0x4F0
 207 /* orig         cns$ei_addr     quadword; */
 208 #define CNS_Q_EI_ADDR           0x4F8
 209 /* orig         cns$fill_syn    quadword; */
 210 #define CNS_Q_FILL_SYN          0x500
 211 /* orig         cns$ld_lock     quadword; */
 212 #define CNS_Q_LD_LOCK           0x508
 213 /* orig         cns$bc_ctl      quadword;       // shadow of on chip bc_ctl  */
 214 #define CNS_Q_BC_CTL            0x510
 215 /* orig         cns$pmctr_ctl   quadword;       // saved frequency select info for performance monitor counter */
 216 #define CNS_Q_PM_CTL            0x518
 217 /* orig         cns$bc_config   quadword;       // shadow of on chip bc_config */
 218 #define CNS_Q_BC_CFG            0x520
 219
 220 /* orig         constant cns$size equals .;
 221  * orig
 222  * orig         constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
 223  * orig         constant pal$impure_specific_size equals (.+7) & %xfff8;
 224  * orig         constant cns$mchksize equals (.+7-#t) & %xfff8;
 225  * orig         constant pal$logout_area        equals pal$impure_specific_size ;
 226  * orig end impure;
 227 */
 228
 229 /* This next set of stuff came from the old code ..pb */
 230 #define CNS_Q_SROM_REV          0x528
 231 #define CNS_Q_PROC_ID           0x530
 232 #define CNS_Q_MEM_SIZE          0x538
 233 #define CNS_Q_CYCLE_CNT         0x540
 234 #define CNS_Q_SIGNATURE         0x548
 235 #define CNS_Q_PROC_MASK         0x550
 236 #define CNS_Q_SYSCTX            0x558
 237
 238
 239
 240 #define MACHINE_CHECK_CRD_BASE 0
 241 #define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8)
 242
 243
 244
 245 /* orig
 246  * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
 247  * orig         SPROCESS bitfield length 1 ;
 248  * orig         FILL_0 bitfield length 3 fill tag $$;
 249  * orig         FRQ2 bitfield length 2 ;
 250  * orig         FRQ1 bitfield length 2 ;
 251  * orig         FRQ0 bitfield length 2 ;
 252  * orig         CTL2 bitfield length 2 ;
 253  * orig         CTL1 bitfield length 2 ;
 254  * orig         CTL0 bitfield length 2 ;
 255  * orig         FILL_1 bitfield length 16 fill tag $$;
 256  * orig         FILL_2 bitfield length 32 fill tag $$;
 257  * orig end EV5PMCTRCTL_BITS;
 258  * orig
 259  * orig end_module $pal_impure;
 260  * orig
 261  * orig module  $pal_logout;
 262  * orig
 263  * orig //
 264  * orig // Start definition of Corrected Error Frame
 265  * orig //
 266  */
 267
 268 /*
 269  * orig aggregate crd_logout struct prefix "" tag "";
 270  */
 271
 272 #ifdef SIMOS
 273 #define pal_logout_area 0x600
 274 #define mchk_crd_base  0
 275 #endif
 276
 277 /* orig         mchk$crd_flag           quadword; */
 278 #define mchk_crd_flag 0
 279 /* orig         mchk$crd_offsets        quadword; */
 280 #define mchk_crd_offsets 8
 281 /* orig
 282  * orig         // Pal-specific information     */
 283 #define mchk_crd_mchk_code 0x10
 284 /* orig         mchk$crd_mchk_code      quadword;
 285  * orig
 286  * orig         // CPU-specific information
 287  * orig         constant mchk$crd_cpu_base equals . ;
 288  * orig         mchk$crd_ei_addr        quadword; */
 289 #define mchk_crd_ei_addr 0x18
 290 /* orig         mchk$crd_fill_syn       quadword; */
 291 #define mchk_crd_fill_syn 0x20
 292 /* orig         mchk$crd_ei_stat        quadword; */
 293 #define mchk_crd_ei_stat 0x28
 294 /* orig         mchk$crd_isr            quadword; */
 295 #define mchk_crd_isr 0x30
 296
 297 /*
 298  * Hacked up constants for the turbolaser build. Hope
 299  * this is moreless correct
 300  */
 301
 302 #define mchk_crd_whami   0x38
 303 #define mchk_crd_tldev   0x40
 304 #define mchk_crd_tlber   0x48
 305 #define mchk_crd_tlesr0  0x50
 306 #define mchk_crd_tlesr1  0x58
 307 #define mchk_crd_tlesr2  0x60
 308 #define mchk_crd_tlesr3  0x68
 309 #define mchk_crd_rsvd    0x70
 310
 311
 312 #ifdef SIMOS
 313 /*
 314  * mchk area seems different for tlaser
 315  */
 316
 317 #define mchk_crd_size   0x80
 318 #define mchk_mchk_base (mchk_crd_size)
 319
 320 #define mchk_tlber      0x0
 321 #define mchk_tlepaerr   0x8
 322 #define mchk_tlepderr   0x10
 323 #define mchk_tlepmerr   0x18
 324
 325
 326 #endif
 327
 328
 329 /* orig
 330  * orig         // System-specific information
 331  * orig         constant mchk$crd_sys_base equals . ;
 332  * orig         constant mchk$crd_size equals (.+7) & %xfff8;
 333  * orig
 334  * orig end crd_logout;
 335  * orig //
 336  * orig // Start definition of Machine check logout Frame
 337  * orig //
 338  * orig aggregate logout struct prefix "" tag "";
 339  * orig         mchk$flag               quadword; */
 340 /* orig         mchk$offsets            quadword; */
 341 /* orig
 342  * orig  // Pal-specific information
 343  * orig         mchk$mchk_code          quadword; */
 344 /*
 345
 346  * orig         mchk$pt quadword dimension 24;
 347  * orig
 348  * orig  // CPU-specific information
 349  * orig         constant mchk$cpu_base equals . ;
 350  * orig         mchk$exc_addr           quadword;
 351  * orig         mchk$exc_sum            quadword;
 352  * orig         mchk$exc_mask           quadword;
 353  * orig         mchk$pal_base           quadword;
 354  * orig         mchk$isr                quadword;
 355  * orig         mchk$icsr               quadword;
 356  * orig         mchk$ic_perr_stat       quadword;
 357  * orig         mchk$dc_perr_stat       quadword;
 358  * orig         mchk$va                 quadword;
 359  * orig         mchk$mm_stat            quadword;
 360  * orig         mchk$sc_addr            quadword;
 361  * orig         mchk$sc_stat            quadword;
 362  * orig         mchk$bc_tag_addr        quadword;
 363  * orig         mchk$ei_addr            quadword;
 364  * orig         mchk$fill_syn           quadword;
 365  * orig         mchk$ei_stat            quadword;
 366  * orig         mchk$ld_lock            quadword;
 367  * orig
 368  * orig         // System-specific information
 369  * orig
 370  * orig         constant mchk$sys_base equals . ;
 371  * orig         mchk$sys_ipr1           quadword        ; // Holder for system-specific stuff
 372  * orig
 373  * orig         constant mchk$size equals (.+7) & %xfff8;
 374  * orig
 375  * orig
 376  * orig         constant mchk$crd_base  equals 0 ;
 377  * orig         constant mchk$mchk_base equals mchk$crd_size ;
 378  * orig
 379  * orig
 380  * orig end logout;
 381  * orig
 382  * orig end_module $pal_logout;
 383 */
 384
 385
 386
 387
 388 /* this is lingering in the old ladbx code but looks like it was from ev4 days.
 389  * This was 0x160 in the old days..pb
 390 */
 391 #define LAF_K_SIZE         MACHINE_CHECK_SIZE
 392 #endif