2 * Copyright (c) 2003, 2004, 2005
3 * The Regents of The University of Michigan
6 * This code is part of the M5 simulator.
8 * Permission is granted to use, copy, create derivative works and
9 * redistribute this software and such derivative works for any
10 * purpose, so long as the copyright notice above, this grant of
11 * permission, and the disclaimer below appear in all copies made; and
12 * so long as the name of The University of Michigan is not used in
13 * any advertising or publicity pertaining to the use or distribution
14 * of this software without specific, written prior authorization.
16 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
17 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
18 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
19 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
22 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
23 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
24 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
25 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
28 * Modified for M5 by: Ali G. Saidi
33 * Copyright 1993 Hewlett-Packard Development Company, L.P.
35 * Permission is hereby granted, free of charge, to any person
36 * obtaining a copy of this software and associated documentation
37 * files (the "Software"), to deal in the Software without
38 * restriction, including without limitation the rights to use, copy,
39 * modify, merge, publish, distribute, sublicense, and/or sell copies
40 * of the Software, and to permit persons to whom the Software is
41 * furnished to do so, subject to the following conditions:
43 * The above copyright notice and this permission notice shall be
44 * included in all copies or substantial portions of the Software.
46 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
49 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
50 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
51 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
52 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
57 #define hw_rei_spe hw_rei
60 #include "ev5_impure.h"
61 #include "ev5_alpha_defs.h"
62 #include "ev5_paldef.h"
63 #include "ev5_osfalpha_defs.h"
64 #include "fromHudsonMacros.h"
65 #include "fromHudsonOsf.h"
66 #include "dc21164FromGasSources.h"
70 #define pt_entInt pt_entint
71 #define pt_entArith pt_entarith
72 #define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8)
73 #define mchk_flag CNS_Q_FLAG
74 #define mchk_sys_base 56
75 #define mchk_cpu_base (CNS_Q_LD_LOCK + 8)
76 #define mchk_offsets CNS_Q_EXC_ADDR
77 #define mchk_mchk_code 8
78 #define mchk_ic_perr_stat CNS_Q_ICPERR_STAT
79 #define mchk_dc_perr_stat CNS_Q_DCPERR_STAT
80 #define mchk_sc_addr CNS_Q_SC_ADDR
81 #define mchk_sc_stat CNS_Q_SC_STAT
82 #define mchk_ei_addr CNS_Q_EI_ADDR
83 #define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR
84 #define mchk_fill_syn CNS_Q_FILL_SYN
85 #define mchk_ei_stat CNS_Q_EI_STAT
86 #define mchk_exc_addr CNS_Q_EXC_ADDR
87 #define mchk_ld_lock CNS_Q_LD_LOCK
88 #define osfpcb_q_Ksp pcb_q_ksp
89 #define pal_impure_common_size ((0x200 + 7) & 0xfff8)
91 #if defined(BIG_TSUNAMI)
93 #define IPIQ_addr 0x800
95 #define IPIR_addr 0x840
97 #define RTC_addr 0x880
100 #elif defined(TSUNAMI)
102 #define IPIQ_addr 0x080
103 #define IPIQ_shift 12
104 #define IPIR_addr 0x080
106 #define RTC_addr 0x080
108 #define DIR_addr 0xa0
109 #elif defined(TLASER)
112 #error Must define BIG_TSUNAMI, TSUNAMI, or TLASER
115 #define ALIGN_BLOCK \
118 #define ALIGN_BRANCH \
126 // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
127 // XXX the following is 'made up'
130 // XXX bugnion not sure how to align 'quad'
138 #define GET_IMPURE(_r) mfpr _r,pt_impure
139 #define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2)
142 #define BIT(_x) (1<<(_x))
145 // System specific code - beh model version
149 // SYS_CFLUSH - Cache flush
150 // SYS_CSERVE - Console service
151 // SYS_WRIPIR - interprocessor interrupts
152 // SYS_HALT_INTERRUPT - Halt interrupt
153 // SYS_PASSIVE_RELEASE - Interrupt, passive release
154 // SYS_INTERRUPT - Interrupt
159 // Macro to read TLINTRSUMx
161 // Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register
163 // Assumed register usage:
164 // rsum TLINTRSUMx contents
165 // raddr node space address
166 // scratch scratch register
168 #define Read_TLINTRSUMx(_rsum, _raddr, _scratch) \
170 mfpr _scratch, pt_whami; /* Get our whami (VID) */ \
171 extbl _scratch, 1, _scratch; /* shift down to bit 0 */ \
172 lda _raddr, 0xff88(zero); /* Get base node space address bits */ \
173 sll _raddr, 24, _raddr; /* Shift up to proper position */ \
174 srl _scratch, 1, _rsum; /* Shift off the cpu number */ \
175 sll _rsum, 22, _rsum; /* Get our node offset */ \
176 addq _raddr, _rsum, _raddr; /* Get our base node space address */ \
178 lda _raddr, 0x1180(_raddr); \
180 1: lda _raddr, 0x11c0(_raddr); \
181 2: ldl_p _rsum, 0(_raddr) /* read the right tlintrsum reg */
184 // Macro to write TLINTRSUMx
186 // Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register
188 // Assumed register usage:
189 // rsum TLINTRSUMx write data
190 // raddr node space address
191 // scratch scratch register
193 #define Write_TLINTRSUMx(_rsum,_raddr,_whami) \
195 mfpr _whami, pt_whami; /* Get our whami (VID) */ \
196 extbl _whami, 1, _whami; /* shift down to bit 0 */ \
197 lda _raddr, 0xff88(zero); /* Get base node space address bits */ \
198 sll _raddr, 24, _raddr; /* Shift up to proper position */ \
200 lda _raddr, 0x1180(_raddr); \
202 1: lda _raddr, 0x11c0(_raddr); \
203 2: srl _whami, 1, _whami; /* Get our node offset */ \
204 addq _raddr, _whami, _raddr; /* Get our base node space address */ \
206 stq_p _rsum, 0(_raddr); /* write the right tlintrsum reg */ \
207 ldq_p _rsum, 0(_raddr); /* dummy read to tlintrsum */ \
208 bis _rsum, _rsum, _rsum /* needed to complete the ldqp above */
212 // Macro to determine highest priority TIOP Node ID from interrupt pending mask
214 // Assumed register usage:
215 // rmask - TLINTRSUMx contents, shifted to isolate IOx bits
216 // rid - TLSB Node ID of highest TIOP
218 #define Intr_Find_TIOP(_rmask,_rid) \
219 srl _rmask,3,_rid; /* check IOP8 */ \
220 blbc _rid,1f; /* not IOP8 */ \
221 lda _rid,8(zero); /* IOP8 */ \
223 1: srl _rmask,3,_rid; /* check IOP7 */ \
224 blbc _rid, 2f; /* not IOP7 */ \
225 lda _rid, 7(r31); /* IOP7 */ \
227 2: srl _rmask, 2, _rid; /* check IOP6 */ \
228 blbc _rid, 3f; /* not IOP6 */ \
229 lda _rid, 6(r31); /* IOP6 */ \
231 3: srl _rmask, 1, _rid; /* check IOP5 */ \
232 blbc _rid, 4f; /* not IOP5 */ \
233 lda _rid, 5(r31); /* IOP5 */ \
235 4: srl _rmask, 0, _rid; /* check IOP4 */ \
236 blbc _rid, 5f; /* not IOP4 */ \
237 lda r14, 4(r31); /* IOP4 */ \
239 5: lda r14, 0(r31); /* passive release */ \
243 // Macro to calculate base node space address for given node id
245 // Assumed register usage:
246 // rid - TLSB node id
247 // raddr - base node space address
248 #define Get_TLSB_Node_Address(_rid,_raddr) \
249 sll _rid, 22, _rid; \
250 lda _raddr, 0xff88(zero); \
251 sll _raddr, 24, _raddr; \
252 addq _raddr, _rid, _raddr
255 #define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
256 lda _rs1, tlep_##_tlepreg(zero); \
257 or _rs1, _nodebase, _rs1; \
258 ldl_p _rs1, 0(_rs1); \
259 stl_p _rs, mchk_##_tlepreg(_rlog) /* store in frame */
261 #define OSFmchk_TLEPstore(_tlepreg) \
262 OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
264 #define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
265 lda _rs1, tlep_##_tlepreg(zero); \
266 or _rs1, _nodebase, _rs1; \
267 ldl_p _rs1, 0(_rs1); \
268 stl_p _rs, mchk_crd_##_tlepreg(_rlog)
270 #define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
271 lda _rs1, tlsb_##_tlepreg(zero); \
272 or _rs1, _nodebase, _rs1; \
273 ldl_p _rs1, 0(_rs1); \
274 stl_p _rs,mchk_crd_##_tlepreg(_rlog)
276 #define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
277 lda _rs1,tlsb_##_tlepreg(zero); \
278 or _rs1, _nodebase,_rs1; \
279 ldl_p _rs1, 0(_rs1); \
280 stl_p _rs, mchk_crd_##_tlepreg(_rlog); \
283 #define OSFcrd_TLEPstore(_tlepreg) \
284 OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
285 #define OSFcrd_TLEPstore_tlsb(_tlepreg) \
286 OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
287 #define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) \
288 OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
291 #define save_pcia_intr(_irq) \
292 and r13, 0xf, r25; /* isolate low 4 bits */ \
293 addq r14, 4, r14; /* format the TIOP Node id field */ \
294 sll r14, 4, r14; /* shift the TIOP Node id */ \
295 or r14, r25, r10; /* merge Node id/hose/HPC */ \
296 mfpr r14, pt14; /* get saved value */ \
297 extbl r14, _irq, r25; /* confirm none outstanding */ \
298 bne r25, sys_machine_check_while_in_pal; \
299 insbl r10, _irq, r10; /* align new info */ \
300 or r14, r10, r14; /* merge info */ \
301 mtpr r14, pt14; /* save it */ \
302 bic r13, 0xf, r13 /* clear low 4 bits of vector */
305 // wripir - PALcode for wripir instruction
306 // R16 has the processor number.
311 // Convert the processor number to a CPU mask
313 and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported
314 bis r31, 0x1, r16 // get a one
315 sll r16, r14, r14 // shift the bit to the right place
316 #if defined(TSUNAMI) || defined(BIG_TSUNAMI)
317 sll r14,IPIQ_shift,r14
322 // Build the Broadcast Space base address
324 #if defined(TSUNAMI) || defined(BIG_TSUNAMI)
330 lda r16,IPIQ_addr(r16)
331 #elif defined(TLASER)
332 lda r13, 0xff8e(r31) // Load the upper address bits
333 sll r13, 24, r13 // shift them to the top
337 // Send out the IP Intr
339 #if defined(TSUNAMI) || defined(BIG_TSUNAMI)
340 stq_p r14, 0(r16) // Tsunami MISC Register
341 #elif defined(TLASER)
342 stq_p r14, 0x40(r13) // Write to TLIPINTR reg
344 wmb // Push out the store
348 // cflush - PALcode for CFLUSH instruction
352 // R16 - contains the PFN of the page to be flushed
355 // Flush all Dstream caches of 1 entire page
361 // #convert pfn to addr, and clean off <63:20>
362 // #sll r16, <page_offset_size_bits>+<63-20>>, r12
363 sll r16, page_offset_size_bits+(63-20),r12
365 // #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
366 // # stolen from srcmax code. XXX bugnion
367 lda r13, 0x10(r31) // assume 16Mbytes of cache
368 sll r13, 20, r13 // convert to bytes
371 srl r12, 63-20, r12 // shift back to normal position
372 xor r12, r13, r12 // xor addr<18>
374 or r31, 8192/(32*8), r13 // get count of loads
378 subq r13, 1, r13 // decr counter
379 mfpr r25, ev5__intid // Fetch level of interruptor
381 ldq_p r31, 32*0(r12) // do a load
382 ldq_p r31, 32*1(r12) // do next load
384 ldq_p r31, 32*2(r12) // do next load
385 ldq_p r31, 32*3(r12) // do next load
387 ldq_p r31, 32*4(r12) // do next load
388 ldq_p r31, 32*5(r12) // do next load
390 ldq_p r31, 32*6(r12) // do next load
391 ldq_p r31, 32*7(r12) // do next load
393 mfpr r14, ev5__ipl // Fetch current level
394 lda r12, (32*8)(r12) // skip to next cache block addr
396 cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl
397 beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt???
399 bne r13, cflush_loop // loop till done
400 hw_rei // back to user
403 1: // Here if interrupted
405 subq r12, 4, r12 // Backup PC to point to CFLUSH
410 mfpr r31, pt0 // Pad exc_addr write
416 // sys_cserve - PALcode for CSERVE instruction
419 // Various functions for private use of console software
421 // option selector in r0
422 // arguments in r16....
429 // args, are as for normal STQ_P/LDQ_P in VMS PAL
432 // r16 = detination PA to dump tb's to.
434 // r0<0> = 1, success
435 // r0<0> = 0, failure, or option not supported
436 // r0<63:1> = (generally 0, but may be function dependent)
437 // r0 - load data on ldq_p
442 /* taken from scrmax */
443 cmpeq r18, CSERVE_K_RD_IMPURE, r0
444 bne r0, Sys_Cserve_Rd_Impure
446 cmpeq r18, CSERVE_K_JTOPAL, r0
447 bne r0, Sys_Cserve_Jtopal
451 hw_rei // and back we go
453 Sys_Cserve_Rd_Impure:
454 mfpr r0, pt_impure // Get base of impure scratch area.
460 bic a0, 3, t8 // Clear out low 2 bits of address
461 bis t8, 1, t8 // Or in PAL mode bit
468 ldq_p r0,0(r17) // get the data
469 nop // pad palshadow write
471 hw_rei // and back we go
477 stq_p r18, 0(r17) // store the data
478 lda r0,17(r31) // bogus
479 hw_rei // and back we go
484 ldq r16, 0(r17) // restore r16
485 ldq r17, 8(r17) // restore r17
486 lda r0, hlt_c_callback(r31)
487 br r31, sys_enter_console
499 // DTB PTEs - 64 entries
500 addq r31, 64, r0 // initialize loop counter
503 1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp
504 mfpr r12, ev5__dtb_pte // read out next pte to reg file
506 subq r0, 1, r0 // decrement loop counter
507 nop // Pad - no Mbox instr in cycle after mfpr
509 stq_p r12, 0(r16) // store out PTE
510 addq r16, 8 ,r16 // increment pointer
515 // ITB PTEs - 48 entries
516 addq r31, 48, r0 // initialize loop counter
519 2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp
520 mfpr r12, ev5__itb_pte // read out next pte to reg file
522 subq r0, 1, r0 // decrement loop counter
525 stq_p r12, 0(r16) // store out PTE
526 addq r16, 8 ,r16 // increment pointer
529 or r31, 1, r0 // set success
531 hw_rei // and back we go
535 // SYS_INTERRUPT - Interrupt processing code
539 // ps, sp and gp are updated
540 // r12, r14 - available
541 // r13 - INTID (new EV5 IPL)
543 // r16, r17, r18 - available
546 EXPORT(sys_interrupt)
547 cmpeq r13, 31, r12 // Check for level 31 interrupt
548 bne r12, sys_int_mchk_or_crd // machine check or crd
550 cmpeq r13, 30, r12 // Check for level 30 interrupt
551 bne r12, sys_int_powerfail // powerfail
553 cmpeq r13, 29, r12 // Check for level 29 interrupt
554 bne r12, sys_int_perf_cnt // performance counters
556 cmpeq r13, 23, r12 // Check for level 23 interrupt
557 bne r12, sys_int_23 // IPI in Tsunami
559 cmpeq r13, 22, r12 // Check for level 22 interrupt
560 bne r12, sys_int_22 // timer interrupt
562 cmpeq r13, 21, r12 // Check for level 21 interrupt
563 bne r12, sys_int_21 // I/O
565 cmpeq r13, 20, r12 // Check for level 20 interrupt
566 bne r12, sys_int_20 // system error interrupt
567 // (might be corrected)
569 mfpr r14, exc_addr // ooops, something is wrong
570 br r31, pal_pal_bug_check_from_int
575 // Routines to handle device interrupts at IPL 23-20.
576 // System specific method to ack/clear the interrupt, detect passive
577 // release, detect interprocessor (22), interval clock (22), corrected
582 // ps, sp and gp are updated
583 // r12, r14 - available
584 // r13 - INTID (new EV5 IPL)
588 // Interrupt has been ack'd/cleared
589 // a0/r16 - signals IO device interrupt
590 // a1/r17 - contains interrupt vector
591 // exit to ent_int address
595 #if defined(TSUNAMI) || defined(BIG_TSUNAMI)
598 or r31,0,r16 // IPI interrupt A0 = 0
599 lda r12,0xf01(r31) // build up an address for the MISC register
603 lda r12,IPIR_addr(r12)
605 mfpr r10, pt_whami // get CPU ID
606 extbl r10, 1, r10 // Isolate just whami bits
607 or r31,0x1,r14 // load r14 with bit to clear
608 sll r14,r10,r14 // left shift by CPU ID
609 sll r14,IPIR_shift,r14
610 stq_p r14, 0(r12) // clear the ipi interrupt
612 br r31, pal_post_interrupt // Notify the OS
617 or r31,1,r16 // a0 means it is a clock interrupt
618 lda r12,0xf01(r31) // build up an address for the MISC register
622 lda r12,RTC_addr(r12)
624 mfpr r10, pt_whami // get CPU ID
625 extbl r10, 1, r10 // Isolate just whami bits
626 or r31,0x1,r14 // load r14 with bit to clear
627 sll r14,r10,r14 // left shift by CPU ID
628 sll r14,RTC_shift,r14 // put the bits in the right position
629 stq_p r14, 0(r12) // clear the rtc interrupt
631 br r31, pal_post_interrupt // Tell the OS
636 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
637 srl r13, 12, r13 // shift down to examine IPL15
639 Intr_Find_TIOP(r13,r14)
642 Get_TLSB_Node_Address(r14,r10)
643 lda r10, 0xa40(r10) // Get base TLILID address
645 ldl_p r13, 0(r10) // Read the TLILID register
646 bne r13, pal_post_dev_interrupt
649 and r13, 0x3, r10 // check for PCIA bits
650 beq r10, pal_post_dev_interrupt // done if nothing set
652 br r31, pal_post_dev_interrupt //
654 1: lda r16, osfint_c_passrel(r31) // passive release
655 br r31, pal_post_interrupt //
661 lda r12,0xf01(r31) // calculate DIRn address
663 ldah r13,DIR_addr(r31)
667 mfpr r13, pt_whami // get CPU ID
668 extbl r13, 1, r13 // Isolate just whami bits
675 and r13,0x1,r14 // grab LSB and shift left 6
677 and r13,0x2,r10 // grabl LSB+1 and shift left 9
680 mskbl r12,0,r12 // calculate DIRn address
687 ldq_p r13, 0(r12) // read DIRn
689 or r31,1,r14 // set bit 55 (ISA Interrupt)
692 and r13, r14, r14 // check if bit 55 is set
693 lda r16,0x900(r31) // load offset for normal into r13
694 beq r14, normal_int // if not compute the vector normally
696 lda r16,0x800(r31) // replace with offset for pic
697 lda r12,0xf01(r31) // build an addr to access PIC
698 sll r12,32,r12 // at f01fc000000
702 ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev
705 //ctlz r13,r14 // count the number of leading zeros
706 // EV5 doesn't have ctlz, but we do, so lets use it
712 subq r10,r14,r17 // subtract from
715 mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit)
718 or r31,3,r16 // a0 means it is a I/O interrupt
720 br r31, pal_post_interrupt
722 #elif defined(TLASER)
725 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
726 srl r13, 22, r13 // shift down to examine IPL17
728 Intr_Find_TIOP(r13,r14)
731 Get_TLSB_Node_Address(r14,r10)
732 lda r10, 0xac0(r10) // Get base TLILID address
734 ldl_p r13, 0(r10) // Read the TLILID register
735 bne r13, pal_post_dev_interrupt
737 1: lda r16, osfint_c_passrel(r31) // passive release
738 br r31, pal_post_interrupt //
743 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
744 srl r13, 6, r14 // check the Intim bit
746 blbs r14, tlep_intim // go service Intim
747 srl r13, 5, r14 // check the IP Int bit
749 blbs r14, tlep_ipint // go service IP Int
750 srl r13, 17, r13 // shift down to examine IPL16
752 Intr_Find_TIOP(r13,r14)
755 Get_TLSB_Node_Address(r14,r10)
756 lda r10, 0xa80(r10) // Get base TLILID address
758 ldl_p r13, 0(r10) // Read the TLILID register
759 bne r13, pal_post_dev_interrupt
762 and r13, 0x3, r10 // check for PCIA bits
763 beq r10, pal_post_dev_interrupt // done if nothing set
765 br r31, pal_post_dev_interrupt //
767 1: lda r16, osfint_c_passrel(r31) // passive release
768 br r31, pal_post_interrupt //
773 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
774 srl r13, 12, r13 // shift down to examine IPL15
776 Intr_Find_TIOP(r13,r14)
779 Get_TLSB_Node_Address(r14,r10)
780 lda r10, 0xa40(r10) // Get base TLILID address
782 ldl_p r13, 0(r10) // Read the TLILID register
783 bne r13, pal_post_dev_interrupt
786 and r13, 0x3, r10 // check for PCIA bits
787 beq r10, pal_post_dev_interrupt // done if nothing set
789 br r31, pal_post_dev_interrupt //
791 1: lda r16, osfint_c_passrel(r31) // passive release
792 br r31, pal_post_interrupt //
797 lda r13, 1(r31) // Duart0 bit
798 Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
800 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
801 blbs r13, tlep_uart0 // go service UART int
803 srl r13, 7, r13 // shift down to examine IPL14
804 Intr_Find_TIOP(r13,r14)
806 beq r14, tlep_ecc // Branch if not IPL14
807 Get_TLSB_Node_Address(r14,r10)
809 lda r10, 0xa00(r10) // Get base TLILID0 address
810 ldl_p r13, 0(r10) // Read the TLILID register
812 bne r13, pal_post_dev_interrupt
815 and r13, 0x3, r10 // check for PCIA bits
816 beq r10, pal_post_dev_interrupt // done if nothing set
818 br r31, pal_post_dev_interrupt //
819 1: lda r16, osfint_c_passrel(r31) // passive release
820 br r31, pal_post_interrupt //
825 lda r13, 0xffb(r31) // get upper GBUS address bits
826 sll r13, 28, r13 // shift up to top
828 lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset)
829 ldq_p r13, 0(r13) // read CSRC
831 lda r13, 0x40(r31) // load Intim bit
832 Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit
834 lda r16, osfint_c_clk(r31) // passive release
835 br r31, pal_post_interrupt // Build the stack frame
840 lda r13, 0x20(r31) // load IP Int bit
841 Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit
843 lda r16, osfint_c_ip(r31) // passive release
844 br r31, pal_post_interrupt // Build the stack frame
849 lda r13, 0xffa(r31) // get upper GBUS address bits
850 sll r13, 28, r13 // shift up to top
852 ldl_p r14, 0x80(r13) // zero pointer register
853 lda r14, 3(r31) // index to RR3
855 stl_p r14, 0x80(r13) // write pointer register
859 ldl_p r14, 0x80(r13) // read RR3
861 srl r14, 5, r10 // is it Channel A RX?
864 srl r14, 4, r10 // is it Channel A TX?
867 srl r14, 2, r10 // is it Channel B RX?
870 srl r14, 1, r10 // is it Channel B TX?
873 lda r8, 0(r31) // passive release
874 br r31, clear_duart0_int // clear tlintrsum and post
879 lda r8, 0x680(r31) // UART0 RX vector
880 br r31, clear_duart0_int // clear tlintrsum and post
885 lda r14, 0x28(r31) // Reset TX Int Pending code
887 stl_p r14, 0x80(r13) // write Channel A WR0
890 lda r8, 0x6c0(r31) // UART0 TX vector
891 br r31, clear_duart0_int // clear tlintrsum and post
896 lda r8, 0x690(r31) // UART1 RX vector
897 br r31, clear_duart0_int // clear tlintrsum and post
902 lda r14, 0x28(r31) // Reset TX Int Pending code
903 stl_p r14, 0(r13) // write Channel B WR0
905 lda r8, 0x6d0(r31) // UART1 TX vector
906 br r31, clear_duart0_int // clear tlintrsum and post
911 lda r13, 1(r31) // load duart0 bit
912 Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
915 or r8, r31, r13 // move vector to r13
916 br r31, pal_post_dev_interrupt // Build the stack frame
920 // lda r16, osfint_c_passrel(r31) // passive release
921 // br r31, pal_post_interrupt //
926 mfpr r14, pt_whami // get our node id
927 extbl r14, 1, r14 // shift to bit 0
929 srl r14, 1, r14 // shift off cpu number
930 Get_TLSB_Node_Address(r14,r10) // compute our nodespace address
932 ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset
933 srl r13, 17, r13 // shift down the CWDE/CRDE bits
935 and r13, 3, r13 // mask the CWDE/CRDE bits
938 ornot r31, r31, r12 // set flag
939 lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code
940 br r31, sys_merge_sys_corr // jump to CRD logout frame code
942 1: lda r16, osfint_c_passrel(r31) // passive release
944 #endif // if TSUNAMI || BIG_TSUNAMI elif TLASER
947 pal_post_dev_interrupt:
948 or r13, r31, r17 // move vector to a1
949 or r31, osfint_c_dev, r16 // a0 signals IO device interrupt
963 // sys_passive_release
964 // Just pretend the interrupt never occurred.
967 EXPORT(sys_passive_release)
968 mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps
971 mfpr r31, pt0 // Pad write to dtb_cm
976 // A powerfail interrupt has been detected. The stack has been pushed.
977 // IPL and PS are updated as well.
979 // I'm not sure what to do here, I'm treating it as an IO device interrupt
985 lda r12, 0xffc4(r31) // get GBUS_MISCR address bits
986 sll r12, 24, r12 // shift to proper position
987 ldq_p r12, 0(r12) // read GBUS_MISCR
988 srl r12, 5, r12 // isolate bit <5>
989 blbc r12, 1f // if clear, no missed mchk
991 // Missed a CFAIL mchk
992 lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
993 sll r13, 24, r13 // shift to proper position
994 lda r14, 0x40(r31) // get bit <6> mask
995 ldq_p r12, 0(r13) // read GBUS$SERNUM
996 or r12, r14, r14 // set bit <6>
997 stq_p r14, 0(r13) // clear GBUS$SERNUM<6>
1001 1: br r31, sys_int_mchk // do a machine check
1003 lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector
1006 lda r16, osfint_c_dev(r31) // a0 to device code
1009 nop // pad exc_addr write
1015 // sys_halt_interrupt
1016 // A halt interrupt has been detected. Pass control to the console.
1020 EXPORT(sys_halt_interrupt)
1022 ldah r13, 0x1800(r31) // load Halt/^PHalt bits
1023 Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits
1025 mtpr r11, dtb_cm // Restore Mbox current mode
1029 lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt
1030 br r31, sys_enter_console // enter the console
1035 // sys_int_mchk_or_crd
1039 // ps, sp and gp are updated
1041 // r13 - INTID (new EV5 IPL)
1044 // r16, r17, r18 - available
1048 sys_int_mchk_or_crd:
1049 srl r25, isr_v_mck, r12
1050 blbs r12, sys_int_mchk
1052 // Not a Machine check interrupt, so must be an Internal CRD interrupt
1055 mb //Clear out Cbox prior to reading IPRs
1056 srl r25, isr_v_crd, r13 //Check for CRD
1057 blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!!
1060 sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd
1061 mtpr r9, ev5__hwint_clr // ack the crd interrupt
1063 or r31, r31, r12 // clear flag
1064 lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code
1067 ldah r14, 0xfff0(r31)
1068 mtpr r0, pt0 // save r0 for scratch
1069 zap r14, 0xE0, r14 // Get Cbox IPR base
1070 mtpr r1, pt1 // save r0 for scratch
1072 ldq_p r0, ei_addr(r14) // EI_ADDR IPR
1073 ldq_p r10, fill_syn(r14) // FILL_SYN IPR
1074 bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub
1076 blbs r12, 1f // no scrubbing for IRQ0 case
1077 // XXX bugnion pvc_jsr crd_scrub_mem, bsr=1
1078 bsr r13, sys_crd_scrub_mem // and go scrub
1080 // ld/st pair in scrub routine will have finished due
1081 // to ibox stall of stx_c. Don't need another mb.
1082 ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
1083 or r8, r31, r12 // Must only be executed once in this flow, and must
1084 br r31, 2f // be after the scrub routine.
1086 1: ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
1087 // For IRQ0 CRD case only - meaningless data.
1089 2: mfpr r13, pt_mces // Get MCES
1090 srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES
1091 blbc r14, 6f // branch if 630
1092 srl r13, mces_v_dsc, r14 // check if 620 reporting disabled
1093 blbc r14, 5f // branch if enabled
1094 or r13, r31, r14 // don't set SCE if disabled
1095 br r31, 8f // continue
1096 5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit
1099 6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled
1100 blbc r14, 7f // branch if enabled
1101 or r13, r31, r14 // don't set PCE if disabled
1102 br r31, 8f // continue
1103 7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit
1105 // Setup SCB if dpc is not set
1106 8: mtpr r14, pt_mces // Store updated MCES
1107 srl r13, mces_v_sce, r1 // Get SCE
1108 srl r13, mces_v_pce, r14 // Get PCE
1109 or r1, r14, r1 // SCE OR PCE, since they share
1110 // the CRD logout frame
1111 // Get base of the logout area.
1112 GET_IMPURE(r14) // addr of per-cpu impure area
1113 GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14)
1115 blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame
1117 // Set the 2nd error flag in the logout area:
1119 lda r1, 3(r31) // Set retry and 2nd error flags
1120 sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword
1121 stl_p r1, mchk_crd_flag+4(r14) // store flag longword
1124 sys_crd_write_logout_frame:
1125 // should only be here if neither the pce or sce bits are set
1128 // Write the mchk code to the logout area
1130 stq_p r9, mchk_crd_mchk_code(r14)
1134 // Write the first 2 quadwords of the logout area:
1136 lda r1, 1(r31) // Set retry flag
1137 sll r1, 63, r9 // Move retry flag to bit 63
1138 lda r1, mchk_crd_size(r9) // Combine retry flag and frame size
1139 stq_p r1, mchk_crd_flag(r14) // store flag/frame size
1142 // Write error IPRs already fetched to the logout area
1144 stq_p r0, mchk_crd_ei_addr(r14)
1145 stq_p r10, mchk_crd_fill_syn(r14)
1146 stq_p r8, mchk_crd_ei_stat(r14)
1147 stq_p r25, mchk_crd_isr(r14)
1149 // Log system specific info here
1152 lda r1, 0xffc4(r31) // Get GBUS$MISCR address
1154 ldq_p r1, 0(r1) // Read GBUS$MISCR
1155 sll r1, 16, r1 // shift up to proper field
1156 mfpr r10, pt_whami // get our node id
1157 extbl r10, 1, r10 // shift to bit 0
1158 or r1, r10, r1 // merge MISCR and WHAMI
1159 stl_p r1, mchk_crd_whami(r14) // write to crd logout area
1160 srl r10, 1, r10 // shift off cpu number
1162 Get_TLSB_Node_Address(r10,r0) // compute our nodespace address
1164 OSFcrd_TLEPstore_tlsb(tldev)
1165 OSFcrd_TLEPstore_tlsb_clr(tlber)
1166 OSFcrd_TLEPstore_tlsb_clr(tlesr0)
1167 OSFcrd_TLEPstore_tlsb_clr(tlesr1)
1168 OSFcrd_TLEPstore_tlsb_clr(tlesr2)
1169 OSFcrd_TLEPstore_tlsb_clr(tlesr3)
1172 mfpr r0, pt0 // restore r0
1173 mfpr r1, pt1 // restore r1
1175 srl r12, ei_stat_v_ei_es, r12
1177 srl r13, mces_v_dsc, r10 // logging enabled?
1179 5: srl r13, mces_v_dpc, r10 // logging enabled?
1180 6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it
1182 // logging not enabled
1183 // Get base of the logout area.
1184 GET_IMPURE(r13) // addr of per-cpu impure area
1185 GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13)
1186 ldl_p r10, mchk_crd_rsvd(r13) // bump counter
1188 stl_p r10, mchk_crd_rsvd(r13)
1190 br r31, sys_crd_dismiss_interrupt // just return
1193 // The stack is pushed. Load up a0,a1,a2 and vector via entInt
1198 sys_crd_post_interrupt:
1199 lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
1200 lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector
1203 lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector
1205 1: subq r31, 1, r18 // get a -1
1208 srl r18, 42, r18 // shift off low bits of kseg addr
1209 mtpr r25, exc_addr // load interrupt vector
1211 sll r18, 42, r18 // shift back into position
1212 or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
1218 // The stack is pushed. Need to back out of it all.
1221 sys_crd_dismiss_interrupt:
1222 br r31, Call_Pal_Rti
1225 // sys_crd_scrub_mem
1227 // r0 = addr of cache block
1229 ALIGN_BLOCK // align for branch target
1231 // now find error in memory, and attempt to scrub that cache block
1232 // This routine just scrubs the failing octaword
1233 // Only need to "touch" one quadword per octaword to accomplish the scrub
1234 srl r0, 39, r8 // get high bit of bad pa
1235 blbs r8, 1f // don't attempt fixup on IO space addrs
1236 nop // needed to align the ldq_pl to octaword boundary
1239 ldq_p r8, 0(r0) // attempt to read the bad memory
1241 // (Note bits 63:40,3:0 of ei_addr
1242 // are set to 1, but as long as
1243 // we are doing a phys ref, should
1245 nop // Needed to keep the Ibox from swapping the ldq_p into E1
1247 stq_p r8, 0(r0) // Store it back if it is still there.
1248 // If store fails, location already
1249 // scrubbed by someone else
1251 nop // needed to align the ldq_p to octaword boundary
1253 lda r8, 0x20(r31) // flip bit 5 to touch next hexaword
1255 nop // needed to align the ldq_p to octaword boundary
1258 ldq_p r8, 0(r0) // attempt to read the bad memory
1260 // (Note bits 63:40,3:0 of ei_addr
1261 // are set to 1, but as long as
1262 // we are doing a phys ref, should
1264 nop // Needed to keep the Ibox from swapping the ldq_p into E1
1266 stq_p r8, 0(r0) // Store it back if it is still there.
1267 // If store fails, location already
1268 // scrubbed by someone else
1270 lda r8, 0x20(r31) // restore r0 to original address
1273 //at this point, ei_stat could be locked due to a new corr error on the ld,
1274 //so read ei_stat to unlock AFTER this routine.
1276 // XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1
1277 1: ret r31, (r13) // and back we go
1281 // sys_int_mchk - MCHK Interrupt code
1283 // Machine check interrupt from the system. Setup and join the
1284 // regular machine check flow.
1291 // pt10 - saved exc_addr
1292 // pt_misc<47:32> - mchk code
1293 // pt_misc<31:16> - scb vector
1294 // r14 - base of Cbox IPRs in IO space
1295 // MCES<mchk> is set
1299 lda r14, mchk_c_sys_hrd_error(r31)
1302 addq r14, 1, r14 // Flag as interrupt
1305 sll r14, 32, r14 // Move mchk code to position
1306 mtpr r12, pt10 // Stash exc_addr
1308 mfpr r12, pt_misc // Get MCES and scratch
1309 mtpr r0, pt0 // Stash for scratch
1311 zap r12, 0x3c, r12 // Clear scratch
1312 blbs r12, sys_double_machine_check // MCHK halt if double machine check
1314 or r12, r14, r12 // Combine mchk code
1315 lda r14, scb_v_sysmchk(r31) // Get SCB vector
1317 sll r14, 16, r14 // Move SCBv to position
1318 or r12, r14, r14 // Combine SCBv
1320 bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
1321 mtpr r14, pt_misc // Save mchk code!scbv!whami!mces
1323 ldah r14, 0xfff0(r31)
1324 mtpr r1, pt1 // Stash for scratch
1326 zap r14, 0xE0, r14 // Get Cbox IPR base
1332 br r31, sys_mchk_collect_iprs // Join common machine check flow
1336 // sys_int_perf_cnt - Performance counter interrupt code
1338 // A performance counter interrupt has been detected. The stack
1339 // has been pushed. IPL and PS are updated as well.
1341 // on exit to interrupt entry point ENTINT::
1342 // a0 = osfint$c_perf
1343 // a1 = scb$v_perfmon (650)
1344 // a2 = 0 if performance counter 0 fired
1345 // a2 = 1 if performance counter 1 fired
1346 // a2 = 2 if performance counter 2 fired
1347 // (if more than one counter overflowed, an interrupt will be
1348 // generated for each counter that overflows)
1353 sys_int_perf_cnt: // Performance counter interrupt
1354 lda r17, scb_v_perfmon(r31) // a1 to interrupt vector
1357 lda r16, osfint_c_perf(r31) // a0 to perf counter code
1360 //isolate which perf ctr fired, load code in a2, and ack
1362 or r31, r31, r18 // assume interrupt was pc0
1364 srl r25, isr_v_pc1, r25 // isolate
1365 cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14
1367 srl r25, 1, r25 // get pc2
1368 cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14
1370 lda r25, 1(r31) // get a one
1373 sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt
1381 // sys_reset - System specific RESET code
1385 // Entry state on trap:
1387 // r2 = base of scratch area
1389 // and the following 3 if init_cbox is enabled:
1394 // Entry state on switch:
1403 // mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load
1404 mtpr r31, itb_ia // clear the ITB
1405 mtpr r31, dtb_ia // clear the DTB
1407 lda r1, -8(r1) // point to start of code
1408 mtpr r1, pal_base // initialize PAL_BASE
1411 mtpr r31, astrr // stop ASTs
1412 mtpr r31, aster // stop ASTs
1413 mtpr r31, sirr // clear software interrupts
1415 mtpr r0, pt1 // r0 is whami (unless we entered via swp)
1417 ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero)
1420 sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable>
1421 or r0, r1, r1 // Set the bit
1423 mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable,
1424 // super page enabled, correct read per assembly option
1427 lda r1,BIT(mcsr_v_sp1)(zero)
1429 mtpr r1, mcsr // MCSR - Super page enabled
1430 lda r1, BIT(dc_mode_v_dc_ena)(r31)
1432 // mtpr r1, dc_mode // turn Dcache on
1435 mfpr r31, pt0 // No Mbox instr in 1,2,3,4
1439 mtpr r31, dc_flush // flush Dcache
1441 // build PS (IPL=7,CM=K,VMM=0,SW=0)
1442 lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
1444 mtpr r1, ipl // set internal <ipl>=1F
1445 mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy
1446 mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy
1448 // Create the PALtemp pt_intmask
1450 // OSF IPL EV5 internal IPL(hex) note
1457 // 6 1E device,performance counter, powerfail
1461 ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
1465 ldah r1, 0x1402(r1) // Create lower lw of int_mask
1468 mtpr r1, pt_intmask // Stash in PALtemp
1470 // Unlock a bunch of chip internal IPRs
1471 mtpr r31, exc_sum // clear out exeception summary and exc_mask
1472 mfpr r31, va // unlock va, mmstat
1473 lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero)
1475 mtpr r8, icperr_stat // Clear Icache parity error & timeout status
1476 lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
1478 mtpr r8, dcperr_stat // Clear Dcache parity error status
1480 rc r0 // clear intr_flag
1484 srl r0, pt_misc_v_switch, r1
1485 blbs r1, sys_reset_switch // see if we got here from swppal
1487 // Rest of the "real" reset flow
1493 sll r1, hwint_clr_v_pc0c, r1
1494 mtpr r1, hwint_clr // Clear hardware interrupt requests
1496 lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
1497 mfpr r0, pt1 // get whami
1498 insbl r0, 1, r0 // isolate whami in correct pt_misc position
1499 or r0, r1, r1 // combine whami and mces
1500 mtpr r1, pt_misc // store whami and mces, swap bit clear
1502 zapnot r3, 1, r0 // isolate halt code
1503 mtpr r0, pt0 // save entry type
1506 or r31, 1, r9 // get a one
1507 sll r9, 32, r9 // shift to <32>
1508 mtpr r31, cc // clear Cycle Counter
1509 mtpr r9, cc_ctl // clear and enable the Cycle Counter
1510 mtpr r31, pt_scc // clear System Cycle Counter
1514 mtpr r31, maf_mode // no mbox instructions for 3 cycles
1515 or r31, 1, r1 // get bogus scbb value
1516 mtpr r1, pt_scbb // load scbb
1517 mtpr r31, pt_prbr // clear out prbr
1518 #if defined(TSUNAMI) || defined(BIG_TSUNAMI)
1519 // yes, this is ugly, but you figure out a better
1520 // way to get the address of the kludge_initial_pcbb
1521 // in r1 with an uncooperative assembler --ali
1522 br r1, kludge_getpcb_addr
1523 br r31, kludge_initial_pcbb
1531 #elif defined(TLASER)
1532 // or zero,kludge_initial_pcbb,r1
1533 GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
1535 mtpr r1, pt_pcbb // load pcbb
1536 lda r1, 2(r31) // get a two
1537 sll r1, 32, r1 // gen up upper bits
1541 // Performance counters
1544 // Clear pmctr_ctl in impure area
1547 ldah r14, 0xfff0(r31)
1548 zap r14, 0xE0, r14 // Get Cbox IPR base
1550 stq_p r31, 0(r13) // Clear lock_flag
1552 mfpr r0, pt0 // get entry type
1553 br r31, sys_enter_console // enter the cosole
1563 sll r9, pt_misc_v_switch, r9
1564 bic r0, r9, r0 // clear switch bit
1567 rpcc r1 // get cyccounter
1569 ldq_p r22, osfpcb_q_fen(r18) // get new fen/pme
1570 ldl_p r23, osfpcb_l_cc(r18) // get cycle counter
1571 ldl_p r24, osfpcb_l_asn(r18) // get new asn
1574 ldq_p r25, osfpcb_q_Mmptr(r18)// get new mmptr
1575 sll r25, page_offset_size_bits, r25 // convert pfn to pa
1576 mtpr r25, pt_ptbr // load the new mmptr
1577 mtpr r18, pt_pcbb // set new pcbb
1579 bic r17, 3, r17 // clean use pc
1580 mtpr r17, exc_addr // set new pc
1584 ldq_p r30, osfpcb_q_Usp(r18) // get new usp
1585 mtpr r30, pt_usp // save usp
1587 sll r24, dtb_asn_v_asn, r8
1589 sll r24, itb_asn_v_asn, r24
1592 mfpr r25, icsr // get current icsr
1594 sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position
1595 bic r25, r24, r25 // clean out old fpe
1596 and r22, 1, r22 // isolate new fen bit
1597 sll r22, icsr_v_fpe, r22
1598 or r22, r25, r25 // or in new fpe
1599 mtpr r25, icsr // update ibox ipr
1601 subl r23, r1, r1 // gen new cc offset
1602 insll r1, 4, r1 // << 32
1603 mtpr r1, cc // set new offset
1605 or r31, r31, r0 // set success
1606 ldq_p r30, osfpcb_q_Ksp(r18) // get new ksp
1607 mfpr r31, pt0 // stall
1611 //sys_machine_check - Machine check PAL
1612 // A machine_check trap has occurred. The Icache has been flushed.
1617 EXPORT(sys_machine_check)
1618 // Need to fill up the refill buffer (32 instructions) and
1619 // then flush the Icache again.
1620 // Also, due to possible 2nd Cbox register file write for
1621 // uncorrectable errors, no register file read or write for 7 cycles.
1624 .long 0x4000054 // call M5 Panic
1625 mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites
1638 // 10 instructions// 5 cycles
1646 // Register file can now be written
1647 lda r0, scb_v_procmchk(r31) // SCB vector
1648 mfpr r13, pt_mces // Get MCES
1649 sll r0, 16, r0 // Move SCBv to correct position
1650 bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
1653 zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word
1658 or r14, r0, r14 // Insert new SCB vector
1659 lda r0, mchk_c_proc_hrd_error(r31) // MCHK code
1662 sll r0, 32, r0 // Move MCHK code to correct position
1664 or r14, r0, r14 // Insert new MCHK code
1665 mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv
1667 ldah r14, 0xfff0(r31)
1668 mtpr r1, pt1 // Stash for scratch - 30 instructions
1670 zap r14, 0xE0, r14 // Get Cbox IPR base
1671 mtpr r12, pt10 // Stash exc_addr
1675 mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed.
1676 blbs r13, sys_double_machine_check // MCHK halt if double machine check
1681 // Look for the powerfail cases here....
1683 srl r4, isr_v_pfl, r4
1684 blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending
1685 lda r4, 0xffc4(r31) // get GBUS$MISCR address bits
1686 sll r4, 24, r4 // shift to proper position
1687 ldq_p r4, 0(r4) // read GBUS$MISCR
1688 srl r4, 5, r4 // isolate bit <5>
1689 blbc r4, sys_mchk_collect_iprs // skip if already cleared
1690 // No missed CFAIL mchk
1691 lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits
1692 sll r5, 24, r5 // shift to proper position
1693 lda r6, 0x40(r31) // get bit <6> mask
1694 ldq_p r4, 0(r5) // read GBUS$SERNUM
1695 or r4, r6, r6 // set bit <6>
1696 stq_p r6, 0(r5) // clear GBUS$SERNUM<6>
1702 // Start to collect the IPRs. Common entry point for mchk flows.
1710 // pt10 - saved exc_addr
1711 // pt_misc<47:32> - mchk code
1712 // pt_misc<31:16> - scb vector
1713 // r14 - base of Cbox IPRs in IO space
1714 // r0, r1, r4, r5, r6, r12, r13, r25 - available
1715 // r8, r9, r10 - available as all loads are physical
1716 // MCES<mchk> is set
1720 EXPORT(sys_mchk_collect_iprs)
1721 .long 0x4000054 // call M5 Panic
1722 //mb // MB before reading Scache IPRs
1723 mfpr r1, icperr_stat
1725 mfpr r8, dcperr_stat
1726 mtpr r31, dc_flush // Flush the Dcache
1728 mfpr r31, pt0 // Pad Mbox instructions from dc_flush
1733 ldq_p r9, sc_addr(r14) // SC_ADDR IPR
1734 bis r9, r31, r31 // Touch ld to make sure it completes before
1736 ldq_p r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR
1738 ldq_p r12, ei_addr(r14) // EI_ADDR IPR
1739 ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR
1740 ldq_p r0, fill_syn(r14) // FILL_SYN IPR
1741 bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
1742 bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT
1743 ldq_p r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
1744 ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked
1750 // Look for nonretryable cases
1752 // r5<0> = 1 means retryable
1753 // r4, r6, and r14 are available for scratch
1758 bis r31, r31, r5 // Clear local retryable flag
1759 srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits
1762 sll r4, icperr_stat_v_tmr, r4
1763 and r1, r4, r4 // Timeout reset
1764 bne r4, sys_cpu_mchk_not_retryable
1766 and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked
1767 bne r4, sys_cpu_mchk_not_retryable
1770 sll r4, sc_stat_v_sc_scnd_err, r4
1771 and r10, r4, r4 // 2nd Scache error occurred
1772 bne r4, sys_cpu_mchk_not_retryable
1775 bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control
1776 // Parity Error, Interface Parity Error, 2nd Error
1779 bne r4, sys_cpu_mchk_not_retryable
1781 // bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
1782 bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
1783 and r25, r4, r4 // Isolate the Uncorrectable Error Bit
1784 // bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
1785 bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
1786 cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error
1787 bne r4, sys_cpu_mchk_not_retryable
1790 and r10, r4, r4 // Isolate the Scache Tag Parity Error bits
1791 bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable
1795 and r10, r4, r4 // Isolate the Scache Data Parity Error bits
1796 srl r10, sc_stat_v_cbox_cmd, r6
1797 and r6, 0x1f, r6 // Isolate Scache Command field
1798 subq r6, 1, r6 // Scache Iread command = 1
1799 cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error
1800 bne r4, sys_cpu_mchk_not_retryable
1802 // Look for the system unretryable cases here....
1804 mfpr r4, isr // mchk_interrupt pin asserted
1805 srl r4, isr_v_mck, r4
1806 blbs r4, sys_cpu_mchk_not_retryable
1811 // Look for retryable cases
1813 // r5<0> = 1 means retryable
1814 // r6 - holds the mchk code
1815 // r4 and r14 are available for scratch
1820 // Within the chip, the retryable cases are Istream errors
1822 sll r4, icperr_stat_v_dpe, r4
1824 cmovne r4, 1, r5 // Retryable if just Icache parity error
1828 and r10, r4, r4 // Isolate the Scache Data Parity Error bits
1829 srl r10, sc_stat_v_cbox_cmd, r14
1830 and r14, 0x1f, r14 // Isolate Scache Command field
1831 subq r14, 1, r14 // Scache Iread command = 1
1832 cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set
1833 cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread
1834 bis r4, r5, r5 // Accumulate
1837 bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
1838 and r25, r4, r4 // Isolate the Uncorrectable Error Bit
1839 and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit
1840 cmovne r4, 1, r4 // r4 = 1 if uncorr error
1841 cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread
1842 bis r4, r5, r5 // Accumulate
1845 extwl r6, 4, r6 // Fetch mchk code
1846 bic r6, 1, r6 // Clear flag from interrupt flow
1847 cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code
1851 // Write the logout frame
1857 // r5<0> - retry flag
1863 // r13 - bc_tag_addr
1865 // r25 - ei_stat (shifted)
1871 // pt10 - saved exc_addr
1875 sys_mchk_write_logout_frame:
1876 // Get base of the logout area.
1877 GET_IMPURE(r14) // addr of per-cpu impure area
1878 GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14)
1880 // Write the first 2 quadwords of the logout area:
1882 sll r5, 63, r5 // Move retry flag to bit 63
1883 lda r4, mchk_size(r5) // Combine retry flag and frame size
1884 stq_p r4, mchk_flag(r14) // store flag/frame size
1885 lda r4, mchk_sys_base(r31) // sys offset
1887 lda r4, mchk_cpu_base(r4) // cpu offset
1888 stq_p r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame
1891 // Write the mchk code to the logout area
1892 // Write error IPRs already fetched to the logout area
1893 // Restore some GPRs from PALtemps
1897 stq_p r6, mchk_mchk_code(r14)
1899 stq_p r1, mchk_ic_perr_stat(r14)
1901 stq_p r8, mchk_dc_perr_stat(r14)
1903 stq_p r9, mchk_sc_addr(r14)
1904 stq_p r10, mchk_sc_stat(r14)
1905 stq_p r12, mchk_ei_addr(r14)
1906 stq_p r13, mchk_bc_tag_addr(r14)
1907 stq_p r0, mchk_fill_syn(r14)
1909 sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position
1910 // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame
1911 ldah r13, 0xfff0(r31)
1912 zapnot r13, 0x1f, r13
1913 ldq_p r13, ei_stat(r13)
1914 sll r13, 64-ei_stat_v_bc_tperr, r13
1915 srl r13, 64-ei_stat_v_bc_tperr, r13
1917 stq_p r25, mchk_ei_stat(r14)
1923 // complete the CPU-specific part of the logout frame
1926 ldah r13, 0xfff0(r31)
1927 zap r13, 0xE0, r13 // Get Cbox IPR base
1928 ldq_p r13, ld_lock(r13) // Get ld_lock IPR
1929 stq_p r13, mchk_ld_lock(r14) // and stash it in the frame
1932 lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
1933 mtpr r8, dcperr_stat // Clear Dcache parity error status
1935 lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31)
1936 mtpr r8, icperr_stat // Clear Icache parity error & timeout status
1938 1: ldq_p r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value
1939 GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value
1940 and r0, r8, r0 // compare
1941 beq r0, 2f // check next case if nothing set
1942 lda r0, mchk_c_retryable_ird(r31) // set new MCHK code
1943 br r31, do_670 // setup new vector
1945 2: ldq_p r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value
1946 GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value
1947 and r0, r8, r0 // compare
1948 beq r0, 3f // check next case if nothing set
1949 lda r0, mchk_c_dcperr(r31) // set new MCHK code
1950 br r31, do_670 // setup new vector
1952 3: ldq_p r8, mchk_sc_stat(r14) // get SC_STAT value
1953 GET_ADDR(r0,0x107ff,r31) // get SC_STAT value
1954 and r0, r8, r0 // compare
1955 beq r0, 4f // check next case if nothing set
1956 lda r0, mchk_c_scperr(r31) // set new MCHK code
1957 br r31, do_670 // setup new vector
1959 4: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value
1960 GET_ADDR(r0,0x30000000,r31) // get EI_STAT value
1961 and r0, r8, r0 // compare
1962 beq r0, 5f // check next case if nothing set
1963 lda r0, mchk_c_bcperr(r31) // set new MCHK code
1964 br r31, do_670 // setup new vector
1966 5: ldl_p r8, mchk_tlber(r14) // get TLBER value
1967 GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value
1968 sll r0, 16, r0 // shift into proper position
1969 GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
1970 or r0, r1, r0 // merge mask values
1971 and r0, r8, r0 // compare
1972 beq r0, 6f // check next case if nothing set
1973 GET_ADDR(r0, 0xfff0, r31) // set new MCHK code
1974 br r31, do_660 // setup new vector
1976 6: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value
1977 GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value
1978 and r0, r8, r0 // compare
1979 beq r0, 7f // check next case if nothing set
1980 GET_ADDR(r0, 0xfffa, r31) // set new MCHK code
1981 br r31, do_660 // setup new vector
1983 7: ldl_p r8, mchk_tlepderr(r14) // get TLEPDERR value
1984 GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value
1985 and r0, r8, r0 // compare
1986 beq r0, 8f // check next case if nothing set
1987 GET_ADDR(r0, 0xfffb, r31) // set new MCHK code
1988 br r31, do_660 // setup new vector
1990 8: ldl_p r8, mchk_tlepmerr(r14) // get TLEPMERR value
1991 GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value
1992 and r0, r8, r0 // compare
1993 beq r0, 9f // check next case if nothing set
1994 GET_ADDR(r0, 0xfffc, r31) // set new MCHK code
1995 br r31, do_660 // setup new vector
1997 9: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value
1998 GET_ADDR(r0,0xb,r31) // get EI_STAT mask value
1999 sll r0, 32, r0 // shift to upper lw
2000 and r0, r8, r0 // compare
2001 beq r0, 1f // check next case if nothing set
2002 GET_ADDR(r0,0xfffd,r31) // set new MCHK code
2003 br r31, do_660 // setup new vector
2005 1: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value
2006 GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value
2007 and r0, r8, r0 // compare
2008 beq r0, cont_logout_frame // check next case if nothing set
2009 GET_ADDR(r0, 0xfffe, r31) // set new MCHK code
2010 br r31, do_660 // setup new vector
2012 do_670: lda r8, scb_v_procmchk(r31) // SCB vector
2014 do_660: lda r8, scb_v_sysmchk(r31) // SCB vector
2016 sll r8, 16, r8 // shift to proper position
2017 mfpr r1, pt_misc // fetch current pt_misc
2018 GET_ADDR(r4,0xffff, r31) // mask for vector field
2019 sll r4, 16, r4 // shift to proper position
2020 bic r1, r4, r1 // clear out old vector field
2021 or r1, r8, r1 // merge in new vector
2022 mtpr r1, pt_misc // save new vector field
2023 stl_p r0, mchk_mchk_code(r14) // save new mchk code
2026 // Restore some GPRs from PALtemps
2031 mfpr r12, pt10 // fetch original PC
2032 blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal
2034 //XXXbugnion pvc_jsr armc, bsr=1
2035 bsr r12, sys_arith_and_mchk // go check for and deal with arith trap
2037 mtpr r31, exc_sum // Clear Exception Summary
2039 mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc
2040 stq_p r25, mchk_exc_addr(r14)
2043 // Set up the km trap
2048 mfpr r25, pt_misc // Check for flag from mchk interrupt
2050 blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow
2052 bis r14, r31, r12 // stash pointer to logout area
2053 mfpr r14, pt10 // get exc_addr
2055 sll r11, 63-3, r25 // get mode to msb
2061 mtpr r30, pt_usp // save user stack
2065 lda sp, 0-osfsf_c_size(sp) // allocate stack space
2068 stq r18, osfsf_a2(sp) // a2
2069 stq r11, osfsf_ps(sp) // save ps
2071 stq r14, osfsf_pc(sp) // save pc
2072 mfpr r25, pt_entint // get the VA of the interrupt routine
2074 stq r16, osfsf_a0(sp) // a0
2075 lda r16, osfint_c_mchk(r31) // flag as mchk in a0
2077 stq r17, osfsf_a1(sp) // a1
2078 mfpr r17, pt_misc // get vector
2080 stq r29, osfsf_gp(sp) // old gp
2081 mtpr r25, exc_addr //
2083 or r31, 7, r11 // get new ps (km, high ipl)
2084 subq r31, 1, r18 // get a -1
2086 extwl r17, 2, r17 // a1 <- interrupt vector
2087 bis r31, ipl_machine_check, r25
2089 mtpr r25, ipl // Set internal ipl
2090 srl r18, 42, r18 // shift off low bits of kseg addr
2092 sll r18, 42, r18 // shift back into position
2093 mfpr r29, pt_kgp // get the kern r29
2095 or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
2096 hw_rei_spe // out to interrupt dispatch routine
2100 // The stack is pushed. Load up a0,a1,a2 and vector via entInt
2104 sys_mchk_stack_done:
2105 lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
2106 lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector
2108 subq r31, 1, r18 // get a -1
2111 srl r18, 42, r18 // shift off low bits of kseg addr
2112 mtpr r25, exc_addr // load interrupt vector
2114 sll r18, 42, r18 // shift back into position
2115 or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
2121 sys_cpu_mchk_not_retryable:
2123 extwl r6, 4, r6 // Fetch mchk code
2124 br r31, sys_mchk_write_logout_frame //
2129 //sys_double_machine_check - a machine check was started, but MCES<MCHK> was
2130 // already set. We will now double machine check halt.
2136 EXPORT(sys_double_machine_check)
2137 lda r0, hlt_c_dbl_mchk(r31)
2138 br r31, sys_enter_console
2141 // sys_machine_check_while_in_pal - a machine check was started,
2142 // exc_addr points to a PAL PC. We will now machine check halt.
2147 sys_machine_check_while_in_pal:
2148 stq_p r12, mchk_exc_addr(r14) // exc_addr has not yet been written
2149 lda r0, hlt_c_mchk_from_pal(r31)
2150 br r31, sys_enter_console
2154 // Check for arithmetic errors and build trap frame,
2155 // but don't post the trap.
2158 // r12 - return address
2159 // r14 - logout frame pointer
2161 // r8,r9,r10 - available except across stq's
2162 // pt0,1,6 - available
2165 // pt10 - new exc_addr
2168 // r14 - logout frame pointer
2172 mfpr r13, ev5__exc_sum
2173 srl r13, exc_sum_v_swc, r13
2174 bne r13, handle_arith_and_mchk
2176 // XXX bugnion pvc$jsr armc, bsr=1, dest=1
2177 ret r31, (r12) // return if no outstanding arithmetic error
2179 handle_arith_and_mchk:
2180 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel
2181 // no virt ref for next 2 cycles
2184 mtpr r1, pt1 // get a scratch reg
2185 and r11, osfps_m_mode, r1 // get mode bit
2187 bis r11, r31, r25 // save ps
2188 beq r1, 1f // if zero we are in kern now
2190 bis r31, r31, r25 // set the new ps
2191 mtpr r30, pt_usp // save user stack
2193 mfpr r30, pt_ksp // get kern stack
2195 mfpr r14, exc_addr // get pc into r14 in case stack writes fault
2197 lda sp, 0-osfsf_c_size(sp) // allocate stack space
2198 mtpr r31, ev5__ps // Set Ibox current mode to kernel
2200 mfpr r1, pt_entArith
2201 stq r14, osfsf_pc(sp) // save pc
2203 stq r17, osfsf_a1(sp)
2204 mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
2206 stq r29, osfsf_gp(sp)
2207 stq r16, osfsf_a0(sp) // save regs
2209 bis r13, r31, r16 // move exc_sum to r16
2210 stq r18, osfsf_a2(sp)
2212 stq r11, osfsf_ps(sp) // save ps
2213 mfpr r29, pt_kgp // get the kern gp
2215 mfpr r14, pt0 // restore logout frame pointer from pt0
2216 bis r25, r31, r11 // set new ps
2218 mtpr r1, pt10 // Set new PC
2221 // XXX bugnion pvc$jsr armc, bsr=1, dest=1
2222 ret r31, (r12) // return if no outstanding arithmetic error
2226 // sys_enter_console - Common PALcode for ENTERING console
2229 // Entered when PAL wants to enter the console.
2230 // usually as the result of a HALT instruction or button,
2231 // or catastrophic error.
2240 // Save all readable machine state, and "call" the console
2247 // In these routines, once the save state routine has been executed,
2248 // the remainder of the registers become scratchable, as the only
2249 // "valid" copy of them is the "saved" copy.
2251 // Any registers or PTs that are modified before calling the save
2252 // routine will have there data lost. The code below will save all
2253 // state, but will loose pt 0,4,5.
2258 EXPORT(sys_enter_console)
2265 /* taken from scrmax, seems like the obvious thing to do */
2275 // sys_exit_console - Common PALcode for ENTERING console
2278 // Entered when console wants to reenter PAL.
2279 // usually as the result of a CONTINUE.
2282 // Regs' on entry...
2287 // Restore all readable machine state, and return to user code.
2297 // clear lock and intr_flags prior to leaving console
2298 rc r31 // clear intr_flag
2299 // lock flag cleared by restore_state
2300 // TB's have been flushed
2302 ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3
2303 ldq_p r1, (cns_gpr+8)(r1) // restore r1
2304 hw_rei_stall // back to user
2307 // kludge_initial_pcbb - PCB for Boot use only
2310 .globl kludge_initial_pcbb
2311 kludge_initial_pcbb: // PCB is 128 bytes long
2333 // SET_SC_BC_CTL subroutine
2335 // Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and
2337 // There must be no outstanding memory references -- istream or
2338 // dstream -- when these registers are written. EV5 prefetcher is
2339 // difficult to turn off. So, this routine needs to be exactly 32
2340 // instructions long// the final jmp must be in the last octaword of a
2341 // page (prefetcher doesn't go across page)
2344 // Register expecations:
2345 // r0 base address of CBOX iprs
2346 // r5 value to set sc_ctl to (flush bit is added in)
2347 // r6 value to set bc_ctl to
2348 // r7 value to set bc_config to
2349 // r10 return address
2350 // r19 old sc_ctl value
2351 // r20 old value of bc_ctl
2352 // r21 old value of bc_config
2353 // r23 flush scache flag
2355 // r17 sc_ctl with flush bit cleared
2360 ret r31, (r10) // return to where we came from
projects / gem5.git / blob