system/alpha/palcode/platform.h

   1 /*
   2  *      VID: [T1.2] PT: [Fri Apr 21 16:47:18 1995] SF: [platform.h]
   3  *       TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
   4  */
   5 #define __PLATFORM_LOADED       1
   6 /*
   7 *****************************************************************************
   8 **                                                                          *
   9 **  Copyright © 1993, 1994                                                 *
  10 **  by Digital Equipment Corporation, Maynard, Massachusetts.               *
  11 **                                                                          *
  12 **  All Rights Reserved                                                     *
  13 **                                                                          *
  14 **  Permission  is  hereby  granted  to  use, copy, modify and distribute   *
  15 **  this  software  and  its  documentation,  in  both  source  code  and   *
  16 **  object  code  form,  and without fee, for the purpose of distribution   *
  17 **  of this software  or  modifications  of this software within products   *
  18 **  incorporating  an  integrated   circuit  implementing  Digital's  AXP   *
  19 **  architecture,  regardless  of the  source of such integrated circuit,   *
  20 **  provided that the  above copyright  notice and this permission notice   *
  21 **  appear  in  all copies,  and  that  the  name  of  Digital  Equipment   *
  22 **  Corporation  not  be  used  in advertising or publicity pertaining to   *
  23 **  distribution of the  document  or  software without specific, written   *
  24 **  prior permission.                                                       *
  25 **                                                                          *
  26 **  Digital  Equipment  Corporation   disclaims  all   warranties  and/or   *
  27 **  guarantees  with  regard  to  this  software,  including  all implied   *
  28 **  warranties of fitness for  a  particular purpose and merchantability,   *
  29 **  and makes  no  representations  regarding  the use of, or the results   *
  30 **  of the use of, the software and documentation in terms of correctness,  *
  31 **  accuracy,  reliability,  currentness  or  otherwise;  and you rely on   *
  32 **  the software, documentation and results solely at your own risk.        *
  33 **                                                                          *
  34 **  AXP is a trademark of Digital Equipment Corporation.                    *
  35 **                                                                          *
  36 *****************************************************************************
  37 **
  38 **  FACILITY:
  39 **
  40 **      DECchip 21164 OSF/1 PALcode
  41 **
  42 **  MODULE:
  43 **
  44 **      platform.h
  45 **
  46 **  MODULE DESCRIPTION:
  47 **
  48 **      Platform specific definitions.
  49 **
  50 **  AUTHOR: Lance Berc (taken from EB164 code)
  51 **
  52 **  CREATION DATE:  14-Jun-1995
  53 **
  54 **  $Id: platform.h,v 1.1.1.1 1997/10/30 23:27:20 verghese Exp $
  55 **
  56 **  MODIFICATION HISTORY:
  57 **
  58 **  $Log: platform.h,v $
  59 **  Revision 1.1.1.1  1997/10/30 23:27:20  verghese
  60 **  current 10/29/97
  61 **
  62  * Revision 1.1  1995/06/14  18:50:42  berc
  63  * Initial revision
  64  *
  65 */
  66
  67 #if !defined(CONSOLE_ENTRY)
  68 #define CONSOLE_ENTRY           0x10000
  69 #endif /* CONSOLE_ENTRY */
  70
  71 #define DEBUGDEATH(c) \
  72         lda     a0, c(zero) ; \
  73         br DebugDeath
  74
  75 #define DEBUGSTORE(c) \
  76         stq_p   t0,0(zero) ; \
  77         stq_p   t1,8(zero) ; \
  78         lda     t0, 0x400(zero) ; \
  79         sll     t0, 29, t0 ; \
  80         ldah    t0, 0x280(t0) ; \
  81 9:      lda     t1, 0x140(t0) ; \
  82         ldl_p   t1, 0(t1) ; \
  83         srl     t1, 16, t1 ; \
  84         and     t1, 0x20, t1 ; \
  85         beq     t1, 9b ; \
  86         lda     t1, c(zero) ; \
  87         stl_p   t1, 0(t0) ; \
  88         mb ; \
  89         ldq_p   t1, 8(zero) ; \
  90         ldq_p   t0, 0(zero)
  91
  92
  93 /*
  94 ** IPL translation table definitions:
  95 **
  96 ** EB164 specific IRQ pins are
  97 **
  98 **  Line   IPL  Source                          OSF/1 IPL
  99 **  ----   ---  ------                          ---------
 100 **  IRQ0   20   Corrected ECC error             7
 101 **  IRQ1   21   PCI/ISA                         3
 102 **  IRQ2   22   Real Time Clock                 5
 103 **  IRQ3   23   SIO NMI, CIA errors             7
 104 **
 105 **  The mask contains one byte for each IPL level, with IPL0 in the
 106 **  least significant (right-most) byte and IPL7 in the most
 107 **  significant (left-most) byte.  Each byte in the mask maps the
 108 **  OSF/1 IPL to the DC21164 IPL.
 109 **
 110 **  OSF/1 IPL   IPL
 111 **  ---------   ---
 112 **      0       0
 113 **      1       1
 114 **      2       2
 115 **      3       21 (to account for PCI/ISA at IPL 21)
 116 **      4       21
 117 **      5       22 (to account for clock at IPL 21)
 118 **      6       30 (to account for powerfail)
 119 **      7       31
 120 */
 121
 122 #define INT_K_MASK_HIGH         0x1F1E1615
 123 #define INT_K_MASK_LOW          0x15020100
 124
 125 #define BYTE_ENABLE_SHIFT       5
 126
 127 /*
 128 ** Dallas DS1287A Real-Time Clock (RTC) Definitions:
 129 */
 130 #define RTCADD 0x160000
 131 #define RTCDAT 0x170000
 132
 133
 134 /*
 135 ** Serial Port (COM) Definitions:
 136 */
 137
 138 #define DLA_K_BRG               12      /* Baud Rate Divisor = 9600 */
 139
 140 #define LSR_V_THRE              5       /* Xmit Holding Register Empty Bit */
 141
 142 #define LCR_M_WLS               3       /* Word Length Select Mask */
 143 #define LCR_M_STB               4       /* Number Of Stop Bits Mask */
 144 #define LCR_M_PEN               8       /* Parity Enable Mask */
 145 #define LCR_M_DLAB              128     /* Divisor Latch Access Bit Mask */
 146
 147 #define LCR_K_INIT              (LCR_M_WLS | LCR_M_STB)
 148
 149 #define MCR_M_DTR               1       /* Data Terminal Ready Mask */
 150 #define MCR_M_RTS               2       /* Request To Send Mask */
 151 #define MCR_M_OUT1              4       /* Output 1 Control Mask */
 152 #define MCR_M_OUT2              8       /* UART Interrupt Mask Enable */
 153
 154 #define MCR_K_INIT              (MCR_M_DTR  | \
 155                                  MCR_M_RTS  | \
 156                                  MCR_M_OUT1 | \
 157                                  MCR_M_OUT2)
 158
 159 /*    CPU Adr[39:29]=0x500 select PCI Mem.      */
 160 #define PCI_MEM   0x400
 161 #define SLOT_D_COM1                (0x140000)
 162 #define SLOT_D_COM2                (0x150000)
 163
 164 #define COM1_RBR (SLOT_D_COM1 | (0x0 << 1)) /* Receive Buffer Register Offset */
 165 #define COM1_THR (SLOT_D_COM1 | (0x0 << 1)) /* Xmit Holding Register Offset */
 166 #define COM1_IER (SLOT_D_COM1 | (0x1 << 1)) /* Interrupt Enable Register Offset */
 167 #define COM1_IIR (SLOT_D_COM1 | (0x2 << 1)) /* Interrupt ID Register Offset */
 168 #define COM1_LCR (SLOT_D_COM1 | (0x3 << 1)) /* Line Control Register Offset */
 169 #define COM1_MCR (SLOT_D_COM1 | (0x4 << 1)) /* Modem Control Register Offset */
 170 #define COM1_LSR (SLOT_D_COM1 | (0x5 << 1)) /* Line Status Register Offset */
 171 #define COM1_MSR (SLOT_D_COM1 | (0x6 << 1)) /* Modem Status Register Offset */
 172 #define COM1_SCR (SLOT_D_COM1 | (0x7 << 1)) /* Scratch Register Offset */
 173 #define COM1_DLL (SLOT_D_COM1 | (0x8 << 1)) /* Divisor Latch (LS) Offset */
 174 #define COM1_DLH (SLOT_D_COM1 | (0x9 << 1)) /* Divisor Latch (MS) Offset */
 175
 176 #define COM2_RBR (SLOT_D_COM2 | (0x0 << 1))
 177 #define COM2_THR (SLOT_D_COM2 | (0x0 << 1))
 178 #define COM2_IER (SLOT_D_COM2 | (0x1 << 1))
 179 #define COM2_IIR (SLOT_D_COM2 | (0x2 << 1))
 180 #define COM2_LCR (SLOT_D_COM2 | (0x3 << 1))
 181 #define COM2_MCR (SLOT_D_COM2 | (0x4 << 1))
 182 #define COM2_LSR (SLOT_D_COM2 | (0x5 << 1))
 183 #define COM2_MSR (SLOT_D_COM2 | (0x6 << 1))
 184 #define COM2_SCR (SLOT_D_COM2 | (0x7 << 1))
 185 #define COM2_DLL (SLOT_D_COM2 | (0x8 << 1))
 186 #define COM2_DLH (SLOT_D_COM2 | (0x9 << 1))
 187
 188
 189 /*
 190 ** Macro to define a port address
 191 */
 192 #define IO_MASK         0x7FFFFFF
 193
 194 /* NOTE ON ADDITIONAL PORT DEFINITION:
 195 **
 196 ** We also need to set bit 39! Since the span between bit 39
 197 ** and the byte enable field is more than 32, we set bit 39 in the
 198 ** port macros.
 199 */
 200
 201 /*
 202 ** Macro to write a byte literal to a specified port
 203 */
 204 #define OutPortByte(port,val,tmp0,tmp1) \
 205         LDLI    (tmp0, port); \
 206         sll     tmp0, BYTE_ENABLE_SHIFT, tmp0; \
 207         lda     tmp1, PCI_MEM(zero); \
 208         sll     tmp1, 29, tmp1; \
 209         bis     tmp0, tmp1, tmp0; \
 210         lda     tmp1, (val)(zero); \
 211         sll     tmp1, 8*(port & 3), tmp1; \
 212         stl_p   tmp1, 0x00(tmp0); \
 213         mb
 214
 215 /*
 216 ** Macro to write a byte from a register to a specified port
 217 */
 218 #define OutPortByteReg(port,reg,tmp0,tmp1) \
 219         LDLI    (tmp0, port); \
 220         sll     tmp0, BYTE_ENABLE_SHIFT, tmp0; \
 221         lda     tmp1, PCI_MEM(zero); \
 222         sll     tmp1, 29, tmp1; \
 223         bis     tmp0, tmp1, tmp0; \
 224         sll     reg, 8*(port & 3), tmp1; \
 225         stl_p   tmp1, 0x00(tmp0); \
 226         mb
 227
 228 /*
 229 ** Macro to write a longword from a register to a specified port
 230 */
 231 #define OutPortLongReg(port,reg,tmp0,tmp1) \
 232         LDLI    (tmp0, port); \
 233         sll     tmp0, BYTE_ENABLE_SHIFT, tmp0; \
 234         lda     tmp1, PCI_MEM(zero); \
 235         sll     tmp1, 29, tmp1; \
 236         bis     tmp0, tmp1, tmp0; \
 237         stl_p   tmp1, 0x18(tmp0); \
 238         mb
 239
 240 /*
 241 ** Macro to read a byte from a specified port
 242 */
 243 #define InPortByte(port,tmp0,tmp1) \
 244         LDLI    (tmp0, port); \
 245         sll     tmp0, BYTE_ENABLE_SHIFT, tmp0; \
 246         lda     tmp1, PCI_MEM(zero); \
 247         sll     tmp1, 29, tmp1; \
 248         bis     tmp0, tmp1, tmp0; \
 249         ldl_p   tmp0, 0x00(tmp0); \
 250         srl     tmp0, (8 * (port & 3)), tmp0; \
 251         zap     tmp0, 0xfe, tmp0