targets/bist.py

   1 import os
   2
   3 from litesata.common import *
   4 from migen.bank import csrgen
   5 from migen.bus import wishbone, csr
   6 from migen.bus import wishbone2csr
   7 from migen.genlib.cdc import *
   8 from migen.genlib.resetsync import AsyncResetSynchronizer
   9 from migen.bank.description import *
  10
  11 from misoclib import identifier
  12
  13 from miscope import MiLa, Term, UART2Wishbone
  14
  15 from litesata.common import *
  16 from litesata.phy import LiteSATAPHY
  17 from litesata import LiteSATA
  18
  19 class _CRG(Module):
  20         def __init__(self, platform):
  21                 self.cd_sys = ClockDomain()
  22                 self.reset = Signal()
  23
  24                 clk200 = platform.request("clk200")
  25                 clk200_se = Signal()
  26                 self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
  27
  28                 pll_locked = Signal()
  29                 pll_fb = Signal()
  30                 pll_sys = Signal()
  31                 self.specials += [
  32                         Instance("PLLE2_BASE",
  33                                 p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  34
  35                                 # VCO @ 1GHz
  36                                 p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
  37                                 p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
  38                                 i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  39
  40                                 # 166MHz
  41                                 p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
  42
  43                                 p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
  44
  45                                 p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
  46
  47                                 p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
  48
  49                                 p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
  50                         ),
  51                         Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  52                         AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
  53                 ]
  54
  55 class GenSoC(Module):
  56         csr_base = 0x00000000
  57         csr_data_width = 32
  58         csr_map = {
  59                 "uart2wb":                      0,
  60                 "identifier":           2,
  61         }
  62         interrupt_map = {}
  63         cpu_type = None
  64         def __init__(self, platform, clk_freq):
  65                 # UART <--> Wishbone bridge
  66                 self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
  67
  68                 # CSR bridge   0x00000000 (shadow @0x00000000)
  69                 self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
  70                 self._wb_masters = [self.uart2wb.wishbone]
  71                 self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
  72                 self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
  73
  74                 # CSR
  75                 self.identifier = identifier.Identifier(0, int(clk_freq), 0)
  76
  77         def add_cpu_memory_region(self, name, origin, length):
  78                 self.cpu_memory_regions.append((name, origin, length))
  79
  80         def add_cpu_csr_region(self, name, origin, busword, obj):
  81                 self.cpu_csr_regions.append((name, origin, busword, obj))
  82
  83         def do_finalize(self):
  84                 # Wishbone
  85                 self.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
  86                         self._wb_slaves, register=True)
  87
  88                 # CSR
  89                 self.csrbankarray = csrgen.BankArray(self,
  90                         lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
  91                         data_width=self.csr_data_width)
  92                 self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
  93                 for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
  94                         self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
  95                 for name, memory, mapaddr, mmap in self.csrbankarray.srams:
  96                         self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
  97
  98 class BISTLeds(Module):
  99         def __init__(self, platform, sata_phy):
 100                 # 1Hz blinking leds (sata_rx and sata_tx clocks)
 101                 sata_rx_led = platform.request("user_led", 0)
 102                 sata_tx_led = platform.request("user_led", 1)
 103
 104                 sata_rx_cnt = Signal(32)
 105                 sata_tx_cnt = Signal(32)
 106
 107                 sata_freq = int(frequencies[sata_phy.revision]*1000*1000)
 108
 109                 self.sync.sata_rx += \
 110                         If(sata_rx_cnt == 0,
 111                                 sata_rx_led.eq(~sata_rx_led),
 112                                 sata_rx_cnt.eq(sata_freq//2)
 113                         ).Else(
 114                                 sata_rx_cnt.eq(sata_rx_cnt-1)
 115                         )
 116
 117                 self.sync.sata_tx += \
 118                         If(sata_tx_cnt == 0,
 119                                 sata_tx_led.eq(~sata_tx_led),
 120                                 sata_tx_cnt.eq(sata_freq//2)
 121                         ).Else(
 122                                 sata_tx_cnt.eq(sata_tx_cnt-1)
 123                         )
 124
 125                 # ready leds (crg and ctrl)
 126                 self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
 127                 self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
 128
 129 class BISTSoC(GenSoC, AutoCSR):
 130         default_platform = "kc705"
 131         csr_map = {
 132                 "sata":         10,
 133         }
 134         csr_map.update(GenSoC.csr_map)
 135
 136         def __init__(self, platform, export_mila=False):
 137                 clk_freq = 166*1000000
 138                 GenSoC.__init__(self, platform, clk_freq)
 139                 self.crg = _CRG(platform)
 140
 141                 # SATA PHY/Core/Frontend
 142                 self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
 143                 self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
 144                 self.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
 145
 146                 # Status Leds
 147                 self.leds = BISTLeds(platform, self.sata_phy)
 148
 149 class BISTSoCDevel(BISTSoC, AutoCSR):
 150         csr_map = {
 151                 "mila":                 11
 152         }
 153         csr_map.update(BISTSoC.csr_map)
 154         def __init__(self, platform, export_mila=False):
 155                 BISTSoC.__init__(self, platform, export_mila)
 156
 157                 self.sata_core_link_rx_fsm_state = Signal(4)
 158                 self.sata_core_link_tx_fsm_state = Signal(4)
 159                 self.sata_core_transport_rx_fsm_state = Signal(4)
 160                 self.sata_core_transport_tx_fsm_state = Signal(4)
 161                 self.sata_core_command_rx_fsm_state = Signal(4)
 162                 self.sata_core_command_tx_fsm_state = Signal(4)
 163
 164                 debug = (
 165                         self.sata_phy.ctrl.ready,
 166
 167                         self.sata_phy.source.stb,
 168                         self.sata_phy.source.data,
 169                         self.sata_phy.source.charisk,
 170
 171                         self.sata_phy.sink.stb,
 172                         self.sata_phy.sink.data,
 173                         self.sata_phy.sink.charisk,
 174
 175                         self.sata.core.command.sink.stb,
 176                         self.sata.core.command.sink.sop,
 177                         self.sata.core.command.sink.eop,
 178                         self.sata.core.command.sink.ack,
 179                         self.sata.core.command.sink.write,
 180                         self.sata.core.command.sink.read,
 181                         self.sata.core.command.sink.identify,
 182
 183                         self.sata.core.command.source.stb,
 184                         self.sata.core.command.source.sop,
 185                         self.sata.core.command.source.eop,
 186                         self.sata.core.command.source.ack,
 187                         self.sata.core.command.source.write,
 188                         self.sata.core.command.source.read,
 189                         self.sata.core.command.source.identify,
 190                         self.sata.core.command.source.failed,
 191                         self.sata.core.command.source.data,
 192
 193                         self.sata_core_link_rx_fsm_state,
 194                         self.sata_core_link_tx_fsm_state,
 195                         self.sata_core_transport_rx_fsm_state,
 196                         self.sata_core_transport_tx_fsm_state,
 197                         self.sata_core_command_rx_fsm_state,
 198                         self.sata_core_command_tx_fsm_state,
 199                 )
 200
 201                 self.mila = MiLa(depth=2048, dat=Cat(*debug))
 202                 self.mila.add_port(Term)
 203                 if export_mila:
 204                         mila_filename = os.path.join("test", "mila.csv")
 205                         self.mila.export(self, debug, mila_filename)
 206
 207         def do_finalize(self):
 208                 BISTSoC.do_finalize(self)
 209                 self.comb += [
 210                         self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state),
 211                         self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state),
 212                         self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state),
 213                         self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state),
 214                         self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state),
 215                         self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
 216                 ]
 217
 218 default_subtarget = BISTSoC