targets/simple.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3 from migen.genlib.io import DifferentialInput
   4
   5 from misoclib.soc import SoC, mem_decoder
   6 from misoclib.com.liteeth.phy import LiteEthPHY
   7 from misoclib.com.liteeth.mac import LiteEthMAC
   8
   9 class _CRG(Module):
  10         def __init__(self, clk_crg):
  11                 self.clock_domains.cd_sys = ClockDomain()
  12                 self.clock_domains.cd_por = ClockDomain(reset_less=True)
  13
  14                 # Power on Reset (vendor agnostic)
  15                 rst_n = Signal()
  16                 self.sync.por += rst_n.eq(1)
  17                 self.comb += [
  18                         self.cd_sys.clk.eq(clk_crg),
  19                         self.cd_por.clk.eq(clk_crg),
  20                         self.cd_sys.rst.eq(~rst_n)
  21                 ]
  22
  23 class BaseSoC(SoC):
  24         def __init__(self, platform, **kwargs):
  25                 SoC.__init__(self, platform,
  26                         clk_freq=int((1/(platform.default_clk_period))*1000000000),
  27                         with_rom=True,
  28                         with_sdram=True, sdram_size=16*1024,
  29                         **kwargs)
  30                 clk_in = platform.request(platform.default_clk_name)
  31                 clk_crg = Signal()
  32                 if hasattr(clk_in, "p"):
  33                         self.specials += DifferentialInput(clk_in.p, clk_in.n, clk_crg)
  34                 else:
  35                         self.comb += clk_crg.eq(clk_in)
  36                 self.submodules.crg = _CRG(clk_crg)
  37
  38 class MiniSoC(BaseSoC):
  39         csr_map = {
  40                 "ethphy":               20,
  41                 "ethmac":               21
  42         }
  43         csr_map.update(BaseSoC.csr_map)
  44
  45         interrupt_map = {
  46                 "ethmac":               2,
  47         }
  48         interrupt_map.update(BaseSoC.interrupt_map)
  49
  50         mem_map = {
  51                 "ethmac":       0x30000000, # (shadow @0xb0000000)
  52         }
  53         mem_map.update(BaseSoC.mem_map)
  54
  55         def __init__(self, platform, **kwargs):
  56                 BaseSoC.__init__(self, platform, **kwargs)
  57
  58                 self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
  59                 self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
  60                 self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  61                 self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
  62
  63 default_subtarget = BaseSoC