5a18b654433c94d26beab862e35219a671578b50
1 from migen
.fhdl
.std
import *
2 from migen
.bus
import wishbone
3 from migen
.genlib
.io
import DifferentialInput
5 from misoclib
.soc
import SoC
, mem_decoder
6 from misoclib
.com
.liteeth
.phy
import LiteEthPHY
7 from misoclib
.com
.liteeth
.mac
import LiteEthMAC
10 def __init__(self
, clk_crg
):
11 self
.clock_domains
.cd_sys
= ClockDomain()
12 self
.clock_domains
.cd_por
= ClockDomain(reset_less
=True)
14 # Power on Reset (vendor agnostic)
16 self
.sync
.por
+= rst_n
.eq(1)
18 self
.cd_sys
.clk
.eq(clk_crg
),
19 self
.cd_por
.clk
.eq(clk_crg
),
20 self
.cd_sys
.rst
.eq(~rst_n
)
24 def __init__(self
, platform
, **kwargs
):
25 SoC
.__init
__(self
, platform
,
26 clk_freq
=int((1/(platform
.default_clk_period
))*1000000000),
28 with_sdram
=True, sdram_size
=16*1024,
30 clk_in
= platform
.request(platform
.default_clk_name
)
32 if hasattr(clk_in
, "p"):
33 self
.specials
+= DifferentialInput(clk_in
.p
, clk_in
.n
, clk_crg
)
35 self
.comb
+= clk_crg
.eq(clk_in
)
36 self
.submodules
.crg
= _CRG(clk_crg
)
38 class MiniSoC(BaseSoC
):
43 csr_map
.update(BaseSoC
.csr_map
)
48 interrupt_map
.update(BaseSoC
.interrupt_map
)
51 "ethmac": 0x30000000, # (shadow @0xb0000000)
53 mem_map
.update(BaseSoC
.mem_map
)
55 def __init__(self
, platform
, **kwargs
):
56 BaseSoC
.__init
__(self
, platform
, **kwargs
)
58 self
.submodules
.ethphy
= LiteEthPHY(platform
.request("eth_clocks"), platform
.request("eth"))
59 self
.submodules
.ethmac
= LiteEthMAC(phy
=self
.ethphy
, dw
=32, interface
="wishbone", with_hw_preamble_crc
=False)
60 self
.add_wb_slave(mem_decoder(self
.mem_map
["ethmac"]), self
.ethmac
.bus
)
61 self
.add_memory_region("ethmac", self
.mem_map
["ethmac"]+0x80000000, 0x2000)
63 default_subtarget
= BaseSoC