targets/simple.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3
   4 from misoclib import spiflash
   5 from misoclib.gensoc import GenSoC
   6
   7 class PowerOnRst(Module):
   8         def __init__(self, cd, overwrite_cd_rst=True):
   9                 self.clock_domains.cd_pwr_on = ClockDomain(reset_less=True)
  10                 self.cd_pwr_on.clk = cd.clk
  11                 self.pwr_on_rst = Signal()
  12
  13                 rst_n = Signal()
  14                 self.sync.pwr_on += rst_n.eq(1)
  15                 self.comb += self.pwr_on_rst.eq(~rst_n)
  16
  17                 if overwrite_cd_rst:
  18                         self.comb += cd.rst.eq(self.pwr_on_rst)
  19
  20 class SimpleSoC(GenSoC):
  21         default_platform = "papilio_pro"
  22
  23         def __init__(self, platform):
  24                 GenSoC.__init__(self, platform,
  25                         clk_freq=32*1000000,
  26                         cpu_reset_address=0x60000)
  27
  28                 # We can't use reset_less as LM32 does require a reset signal
  29                 self.clock_domains.cd_sys = ClockDomain()
  30                 self.submodules += PowerOnRst(self.cd_sys)
  31                 self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
  32
  33                 # BIOS is in SPI flash
  34                 self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
  35                         cmd=0xefef, cmd_width=16, addr_width=24, dummy=4)
  36                 self.flash_boot_address = 0x70000
  37                 self.register_rom(self.spiflash.bus)
  38
  39                 # TODO: use on-board SDRAM instead of block RAM
  40                 sys_ram_size = 32*1024
  41                 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
  42                 self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
  43                 self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
  44
  45 default_subtarget = SimpleSoC