targets/test.py

   1 from migen.fhdl.std import *
   2 from migen.bank import csrgen
   3 from migen.bus import wishbone, csr
   4 from migen.bus import wishbone2csr
   5 from migen.genlib.resetsync import AsyncResetSynchronizer
   6
   7 from miscope.uart2wishbone import UART2Wishbone
   8
   9 from misoclib import identifier
  10 from lib.sata.k7sataphy import K7SATAPHY
  11
  12 class _CRG(Module):
  13         def __init__(self, platform):
  14                 self.clock_domains.cd_sys = ClockDomain()
  15                 self.clock_domains.cd_por = ClockDomain(reset_less=True)
  16
  17                 clk200 = platform.request("clk200")
  18                 clk200_se = Signal()
  19                 self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
  20
  21                 pll_locked = Signal()
  22                 pll_fb = Signal()
  23                 pll_sys = Signal()
  24                 self.specials += [
  25                         Instance("PLLE2_BASE",
  26                                 p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  27
  28                                 # VCO @ 1GHz
  29                                 p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
  30                                 p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
  31                                 i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  32
  33                                 # 166.66MHz
  34                                 p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
  35
  36                                 p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
  37
  38                                 p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
  39
  40                                 p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
  41
  42                                 p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
  43                         ),
  44                         Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  45                         AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
  46                 ]
  47
  48 class UART2WB(Module):
  49         csr_base = 0x00000000
  50         csr_data_width = 8
  51         csr_map = {
  52                 "uart2wb":                      0,
  53                 "identifier":           2,
  54         }
  55         interrupt_map = {}
  56         cpu_type = None
  57         def __init__(self, platform, clk_freq):
  58                 self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq)
  59
  60                 # CSR bridge   0x00000000 (shadow @0x00000000)
  61                 self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
  62                 self._wb_masters = [self.uart2wb.wishbone]
  63                 self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
  64
  65                 # CSR
  66                 self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
  67
  68         def add_wb_master(self, wbm):
  69                 if self.finalized:
  70                         raise FinalizeError
  71                 self._wb_masters.append(wbm)
  72
  73         def add_wb_slave(self, address_decoder, interface):
  74                 if self.finalized:
  75                         raise FinalizeError
  76                 self._wb_slaves.append((address_decoder, interface))
  77
  78         def do_finalize(self):
  79                 # Wishbone
  80                 self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
  81                         self._wb_slaves, register=True)
  82
  83                 # CSR
  84                 self.submodules.csrbankarray = csrgen.BankArray(self,
  85                         lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
  86                         data_width=self.csr_data_width)
  87                 self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
  88
  89 class TestDesign(UART2WB):
  90         default_platform = "kc705"
  91         csr_map = {
  92                 "mila":                         10
  93         }
  94         csr_map.update(UART2WB.csr_map)
  95
  96         def __init__(self, platform, **kwargs):
  97                 clk_freq = 166666*1000
  98                 UART2WB.__init__(self, platform, clk_freq)
  99                 self.submodules.crg = _CRG(platform)
 100
 101                 self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq,
 102                         host=True, default_speed="SATA1")
 103                 self.comb += [
 104                         self.sataphy_host.sink.stb.eq(1),
 105                         self.sataphy_host.sink.d.eq(0x12345678)
 106                 ]
 107
 108                 import os
 109                 from miscope import trigger, miio, mila
 110                 from mibuild.tools import write_to_file
 111                 from migen.fhdl import verilog
 112
 113                 term = trigger.Term(width=64)
 114                 self.submodules.mila = mila.MiLa(width=64, depth=2048, ports=[term], with_rle=True)
 115
 116                 gtx = self.sataphy_host.gtx
 117                 ctrl = self.sataphy_host.ctrl
 118
 119                 mila_dat = (
 120                         gtx.rxresetdone,
 121                         gtx.txresetdone,
 122
 123                         gtx.rxuserrdy,
 124                         gtx.txuserrdy,
 125
 126                         gtx.rxcominitdet,
 127                         gtx.rxcomwakedet,
 128
 129                         gtx.txcomfinish,
 130                         gtx.txcominit,
 131                         gtx.txcomwake,
 132
 133                 )
 134
 135                 self.comb += [
 136                         self.mila.sink.stb.eq(1),
 137                         self.mila.sink.dat.eq(Cat(*mila_dat))
 138                 ]
 139
 140                 try:
 141                         gen_mila_csv = kwargs.pop('gen_mila_csv')
 142                 except:
 143                         gen_mila_csv = False
 144
 145                 if gen_mila_csv:
 146                         r, ns = verilog.convert(self, return_ns=True)
 147                         mila_csv = self.mila.get_csv(mila_dat, ns)
 148                         write_to_file(os.path.join(platform.soc_ext_path, "test", "mila.csv"), mila_csv)
 149
 150 default_subtarget = TestDesign