targets/udpip.py

   1 import os, atexit
   2
   3 from migen.bank import csrgen
   4 from migen.bus import wishbone, csr
   5 from migen.bus import wishbone2csr
   6 from migen.genlib.cdc import *
   7 from migen.genlib.resetsync import AsyncResetSynchronizer
   8 from migen.bank.description import *
   9
  10 from misoclib import identifier
  11
  12 from litescope.common import *
  13 from litescope.bridge.uart2wb import LiteScopeUART2WB
  14 from litescope.frontend.la import LiteScopeLA
  15 from litescope.core.port import LiteScopeTerm
  16
  17 from liteeth.common import *
  18 from liteeth.phy.gmii import LiteEthPHYGMII
  19 from liteeth.core import LiteEthUDPIPCore
  20
  21 class _CRG(Module):
  22         def __init__(self, platform):
  23                 self.clock_domains.cd_sys = ClockDomain()
  24                 self.reset = Signal()
  25
  26                 clk200 = platform.request("clk200")
  27                 clk200_se = Signal()
  28                 self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
  29
  30                 pll_locked = Signal()
  31                 pll_fb = Signal()
  32                 pll_sys = Signal()
  33                 self.specials += [
  34                         Instance("PLLE2_BASE",
  35                                 p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  36
  37                                 # VCO @ 1GHz
  38                                 p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
  39                                 p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
  40                                 i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  41
  42                                 # 166MHz
  43                                 p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
  44
  45                                 p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
  46
  47                                 p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
  48
  49                                 p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
  50
  51                                 p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
  52                         ),
  53                         Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  54                         AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
  55                 ]
  56
  57 class GenSoC(Module):
  58         csr_base = 0x00000000
  59         csr_data_width = 32
  60         csr_map = {
  61                 "bridge":                       0,
  62                 "identifier":           1,
  63         }
  64         interrupt_map = {}
  65         cpu_type = None
  66         def __init__(self, platform, clk_freq):
  67                 self.clk_freq = clk_freq
  68                 # UART <--> Wishbone bridge
  69                 self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
  70
  71                 # CSR bridge   0x00000000 (shadow @0x00000000)
  72                 self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
  73                 self._wb_masters = [self.bridge.wishbone]
  74                 self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
  75                 self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
  76
  77                 # CSR
  78                 self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
  79
  80         def add_cpu_memory_region(self, name, origin, length):
  81                 self.cpu_memory_regions.append((name, origin, length))
  82
  83         def add_cpu_csr_region(self, name, origin, busword, obj):
  84                 self.cpu_csr_regions.append((name, origin, busword, obj))
  85
  86         def do_finalize(self):
  87                 # Wishbone
  88                 self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
  89                         self._wb_slaves, register=True)
  90
  91                 # CSR
  92                 self.submodules.csrbankarray = csrgen.BankArray(self,
  93                         lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
  94                         data_width=self.csr_data_width)
  95                 self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
  96                 for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
  97                         self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
  98                 for name, memory, mapaddr, mmap in self.csrbankarray.srams:
  99                         self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
 100
 101 class UDPIPBISTGeneratorUnit(Module):
 102         def __init__(self):
 103                 self.start = Signal()
 104                 self.src_port = Signal(16)
 105                 self.dst_port = Signal(16)
 106                 self.ip_address = Signal(32)
 107                 self.length = Signal(16)
 108                 self.done = Signal()
 109
 110                 self.source = source = Source(eth_udp_user_description(8))
 111                 ###
 112
 113                 counter = Counter(bits_sign=16)
 114                 self.submodules += counter
 115
 116                 self.fsm = fsm = FSM(reset_state="IDLE")
 117                 self.submodules += fsm
 118                 fsm.act("IDLE",
 119                         self.done.eq(1),
 120                         counter.reset.eq(1),
 121                         If(self.start,
 122                                 NextState("SEND")
 123                         )
 124                 )
 125                 self.comb += [
 126                         source.sop.eq(counter.value == 0),
 127                         source.eop.eq(counter.value == (self.length-1)),
 128                         source.src_port.eq(self.src_port),
 129                         source.dst_port.eq(self.dst_port),
 130                         source.length.eq(self.length),
 131                         source.ip_address.eq(self.ip_address),
 132                         source.data.eq(counter.value)
 133                 ]
 134                 fsm.act("SEND",
 135                         source.stb.eq(1),
 136                         If(source.stb & source.ack,
 137                                 counter.ce.eq(1),
 138                                 If(source.eop,
 139                                         NextState("IDLE")
 140                                 )
 141                         )
 142                 )
 143
 144 class UDPIPBISTGenerator(UDPIPBISTGeneratorUnit, AutoCSR):
 145         def __init__(self):
 146                 self._start = CSR()
 147                 self._src_port = CSRStorage(16)
 148                 self._dst_port = CSRStorage(16)
 149                 self._ip_address = CSRStorage(32)
 150                 self._length = CSRStorage(16)
 151                 self._done = CSRStatus()
 152                 ###
 153                 UDPIPBISTGeneratorUnit.__init__(self)
 154
 155                 self.comb += [
 156                         self.start.eq(self._start.r & self._start.re),
 157                         self.src_port.eq(self._src_port.storage),
 158                         self.dst_port.eq(self._dst_port.storage),
 159                         self.ip_address.eq(self._ip_address.storage),
 160                         self.length.eq(self._length.storage),
 161                         self._done.status.eq(self.done)
 162                 ]
 163
 164 class UDPIPSoC(GenSoC, AutoCSR):
 165         default_platform = "kc705"
 166         csr_map = {
 167                 "ethphy":                       11,
 168                 "udpip_core":           12,
 169                 "bist_generator":       13
 170         }
 171         csr_map.update(GenSoC.csr_map)
 172         def __init__(self, platform):
 173                 clk_freq = 166*1000000
 174                 GenSoC.__init__(self, platform, clk_freq)
 175                 self.submodules.crg = _CRG(platform)
 176
 177                 # Ethernet PHY and UDP/IP
 178                 self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
 179                 self.submodules.udpip_core = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.40"), clk_freq)
 180
 181                 # BIST
 182                 self.submodules.bist_generator = UDPIPBISTGenerator()
 183                 self.comb += [
 184                         Record.connect(self.bist_generator.source, self.udpip_core.sink),
 185                         self.udpip_core.source.ack.eq(1)
 186                 ]
 187
 188 class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
 189         csr_map = {
 190                 "la":                   20
 191         }
 192         csr_map.update(UDPIPSoC.csr_map)
 193         def __init__(self, platform):
 194                 UDPIPSoC.__init__(self, platform)
 195
 196                 self.udpip_core_udp_rx_fsm_state = Signal(4)
 197                 self.udpip_core_udp_tx_fsm_state = Signal(4)
 198                 self.udpip_core_ip_rx_fsm_state = Signal(4)
 199                 self.udpip_core_ip_tx_fsm_state = Signal(4)
 200                 self.udpip_core_arp_rx_fsm_state = Signal(4)
 201                 self.udpip_core_arp_tx_fsm_state = Signal(4)
 202                 self.udpip_core_arp_table_fsm_state = Signal(4)
 203
 204                 debug = (
 205                         self.udpip_core.mac.core.sink.stb,
 206                         self.udpip_core.mac.core.sink.sop,
 207                         self.udpip_core.mac.core.sink.eop,
 208                         self.udpip_core.mac.core.sink.ack,
 209                         self.udpip_core.mac.core.sink.data,
 210
 211                         self.udpip_core.mac.core.source.stb,
 212                         self.udpip_core.mac.core.source.sop,
 213                         self.udpip_core.mac.core.source.eop,
 214                         self.udpip_core.mac.core.source.ack,
 215                         self.udpip_core.mac.core.source.data,
 216
 217                         self.ethphy.sink.stb,
 218                         self.ethphy.sink.sop,
 219                         self.ethphy.sink.eop,
 220                         self.ethphy.sink.ack,
 221                         self.ethphy.sink.data,
 222
 223                         self.ethphy.source.stb,
 224                         self.ethphy.source.sop,
 225                         self.ethphy.source.eop,
 226                         self.ethphy.source.ack,
 227                         self.ethphy.source.data,
 228
 229                         self.udpip_core_udp_rx_fsm_state,
 230                         self.udpip_core_udp_tx_fsm_state,
 231                         self.udpip_core_ip_rx_fsm_state,
 232                         self.udpip_core_ip_tx_fsm_state,
 233                         self.udpip_core_arp_rx_fsm_state,
 234                         self.udpip_core_arp_tx_fsm_state,
 235                         self.udpip_core_arp_table_fsm_state,
 236
 237                 )
 238
 239                 self.submodules.la = LiteScopeLA(debug, 2048)
 240                 self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
 241                 atexit.register(self.exit, platform)
 242
 243         def do_finalize(self):
 244                 UDPIPSoC.do_finalize(self)
 245                 self.comb += [
 246                         self.udpip_core_udp_rx_fsm_state.eq(self.udpip_core.udp.rx.fsm.state),
 247                         self.udpip_core_udp_tx_fsm_state.eq(self.udpip_core.udp.tx.fsm.state),
 248                         self.udpip_core_ip_rx_fsm_state.eq(self.udpip_core.ip.rx.fsm.state),
 249                         self.udpip_core_ip_tx_fsm_state.eq(self.udpip_core.ip.tx.fsm.state),
 250                         self.udpip_core_arp_rx_fsm_state.eq(self.udpip_core.arp.rx.fsm.state),
 251                         self.udpip_core_arp_tx_fsm_state.eq(self.udpip_core.arp.tx.fsm.state),
 252                         self.udpip_core_arp_table_fsm_state.eq(self.udpip_core.arp.table.fsm.state)
 253                 ]
 254
 255         def exit(self, platform):
 256                 if platform.vns is not None:
 257                         self.la.export(platform.vns, "../test/la.csv")
 258
 259 default_subtarget = UDPIPSoC