Merge pull request #1894 from YosysHQ/mingw_fix
[yosys.git] / techlibs / achronix / speedster22i / cells_arith.v
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // NOTE: This is still WIP.
21 (* techmap_celltype = "$alu" *)
22 module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
23 parameter A_SIGNED = 0;
24 parameter B_SIGNED = 0;
25 parameter A_WIDTH = 1;
26 parameter B_WIDTH = 1;
27 parameter Y_WIDTH = 1;
28
29 input [A_WIDTH-1:0] A;
30 input [B_WIDTH-1:0] B;
31 output [Y_WIDTH-1:0] X, Y;
32
33 input CI, BI;
34 //output [Y_WIDTH-1:0] CO;
35 output CO;
36
37 wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
38
39 wire [Y_WIDTH-1:0] A_buf, B_buf;
40 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
41 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
42
43 wire [Y_WIDTH-1:0] AA = A_buf;
44 wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
45 //wire [Y_WIDTH:0] C = {CO, CI};
46 wire [Y_WIDTH+1:0] COx;
47 wire [Y_WIDTH+1:0] C = {COx, CI};
48
49 /* Start implementation */
50 (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
51
52 genvar i;
53 generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
54 if(i==Y_WIDTH-1) begin
55 (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
56 assign CO = COx[Y_WIDTH];
57 end
58 else
59 fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
60 end: slice
61 endgenerate
62 /* End implementation */
63 assign X = AA ^ BB;
64
65 endmodule