techlibs/achronix/speedster22i/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
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   6  *  Permission to use, copy, modify, and/or distribute this software for any
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  18  */
  19 // > c60k28 (Viacheslav, VT) [at] yandex [dot] com
  20 // > Achronix eFPGA technology mapping. User must first simulate the generated \
  21 // > netlist before going to test it on board/custom chip.
  22
  23 // > Input/Output buffers <
  24 // Input buffer map
  25 module \$__inpad (input I, output O);
  26     PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
  27 endmodule
  28 // Output buffer map
  29 module \$__outpad (input I, output O);
  30     PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
  31 endmodule
  32 // > end buffers <
  33
  34 // > Look-Up table <
  35 // > VT: I still think Achronix folks would have chosen a better \
  36 // >     logic architecture.
  37 // LUT Map
  38 module \$lut (A, Y);
  39    parameter WIDTH  = 0;
  40    parameter LUT    = 0;
  41    (* force_downto *)
  42    input [WIDTH-1:0] A;
  43    output            Y;
  44    generate
  45       if (WIDTH == 1) begin
  46            // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
  47          LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
  48            (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
  49       end else
  50       if (WIDTH == 2) begin
  51               LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
  52                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
  53       end else
  54       if(WIDTH == 3) begin
  55               LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
  56                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
  57       end else
  58       if(WIDTH == 4) begin
  59              LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
  60                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
  61       end else
  62            wire _TECHMAP_FAIL_ = 1;
  63    endgenerate
  64 endmodule
  65 // > end LUT <
  66
  67 // > Flops <
  68 // DFF flop
  69 module  \$_DFF_P_ (input D, C, output Q);
  70    DFF _TECHMAP_REPLACE_
  71      (.q(Q), .d(D), .ck(C));
  72 endmodule
  73