2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 // > c60k28 (Viacheslav, VT) [at] yandex [dot] com
20 // > Achronix eFPGA technology mapping. User must first simulate the generated \
21 // > netlist before going to test it on board/custom chip.
23 // > Input/Output buffers <
25 module \$__inpad (input I, output O);
26 PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
29 module \$__outpad (input I, output O);
30 PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
35 // > VT: I still think Achronix folks would have choosen a better \
36 // > logic architecture.
45 // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
46 LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
47 (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
50 LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
51 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
54 LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
55 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
58 LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
59 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
61 wire _TECHMAP_FAIL_ = 1;
68 module \$_DFF_P_ (input D, C, output Q);
70 (.q(Q), .d(D), .ck(C));