techlibs/achronix/speedster22i/cells_map_speedster.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19 // Normal mode DFF negedge clk, negedge reset
  20 module  \$_DFF_N_ (input D, C, output Q);
  21    parameter WYSIWYG="TRUE";
  22    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
  23 endmodule
  24 // Normal mode DFF
  25 module  \$_DFF_P_ (input D, C, output Q);
  26    parameter WYSIWYG="TRUE";
  27    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
  28 endmodule
  29
  30 // Async Active Low Reset DFF
  31 module  \$_DFF_PN0_ (input D, C, R, output Q);
  32    parameter WYSIWYG="TRUE";
  33    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
  34 endmodule
  35 // Async Active High Reset DFF
  36 module  \$_DFF_PP0_ (input D, C, R, output Q);
  37    parameter WYSIWYG="TRUE";
  38    wire R_i = ~ R;
  39    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
  40 endmodule
  41 // Async Active Low Reset DFF
  42 module  \$_DFF_PN0_ (input D, C, R, output Q);
  43    parameter WYSIWYG="TRUE";
  44    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
  45 endmodule
  46 /* */
  47 module  \$__DFFE_PP0 (input D, C, E, R, output Q);
  48    parameter WYSIWYG="TRUE";
  49    wire E_i = ~ E;
  50    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
  51 endmodule
  52
  53 // Input buffer map
  54 module \$__inpad (input I, output O);
  55     PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
  56 endmodule
  57
  58 // Output buffer map
  59 module \$__outpad (input I, output O);
  60     PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
  61 endmodule
  62
  63 // LUT Map
  64 /* 0 -> datac
  65    1 -> cin */
  66 module \$lut (A, Y);
  67    parameter WIDTH  = 0;
  68    parameter LUT    = 0;
  69    input [WIDTH-1:0] A;
  70    output            Y;
  71    generate
  72       if (WIDTH == 1) begin
  73            assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
  74       end else
  75       if (WIDTH == 2) begin
  76               LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
  77       end else
  78       if(WIDTH == 3) begin
  79               LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
  80       end else
  81       if(WIDTH == 4) begin
  82              LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
  83       end else
  84            wire _TECHMAP_FAIL_ = 1;
  85    endgenerate
  86 endmodule //
  87
  88