2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 // > c60k28 (Viacheslav, VT) [at] yandex [dot] com
20 // > Achronix eFPGA technology sim models. User must first simulate the generated \
21 // > netlist before going to test it on board/custom chip.
22 // > Changelog: 1) Removed unused VCC/GND modules
23 // > 2) Altera comments here (?). Removed.
24 // > 3) Reusing LUT sim model, removed wrong wires and parameters.
26 module PADIN (output padout, input padin);
27 assign padout = padin;
30 module PADOUT (output padout, input padin, input oe);
31 assign padout = padin;
35 module LUT4 (output dout,
36 input din0, din1, din2, din3);
38 parameter [15:0] lut_function = 16'hFFFF;
45 assign dataa_w = din0;
46 assign datab_w = din1;
47 assign datac_w = din2;
48 assign datad_w = din3;
52 input dataa, datab, datac, datad;
57 s3 = datad ? mask[15:8] : mask[7:0];
58 s2 = datac ? s3[7:4] : s3[3:0];
59 s1 = datab ? s2[3:2] : s2[1:0];
60 lut_data = dataa ? s1[1] : s1[0];
64 always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
65 combout_rt = lut_data(lut_function, dataa_w, datab_w,
68 assign dout = combout_rt & 1'b1;