techlibs/achronix/speedster22i/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 module VCC (output V);
  21    assign V = 1'b1;
  22 endmodule // VCC
  23
  24 module GND (output G);
  25    assign G = 1'b0;
  26 endmodule // GND
  27
  28 /* Altera MAX10 devices Input Buffer Primitive */
  29 module PADIN (output padout, input padin);
  30    assign padout = padin;
  31 endmodule // fiftyfivenm_io_ibuf
  32
  33 /* Altera MAX10 devices Output Buffer Primitive */
  34 module PADOUT (output padout, input padin, input oe);
  35    assign padout  = padin;
  36    assign oe = oe;
  37 endmodule // fiftyfivenm_io_obuf
  38
  39 /* Altera MAX10 4-input non-fracturable LUT Primitive */
  40 module LUT4 (output dout,
  41              input  din0, din1, din2, din3);
  42
  43 /* Internal parameters which define the behaviour
  44    of the LUT primitive.
  45    lut_mask define the lut function, can be expressed in 16-digit bin or hex.
  46    sum_lutc_input define the type of LUT (combinational | arithmetic).
  47    dont_touch for retiming || carry options.
  48    lpm_type for WYSIWYG */
  49
  50 parameter lut_function = 16'hFFFF;
  51 //parameter dont_touch = "off";
  52 //parameter lpm_type = "fiftyfivenm_lcell_comb";
  53 //parameter sum_lutc_input = "datac";
  54
  55 reg [1:0] lut_type;
  56 reg cout_rt;
  57 reg combout_rt;
  58 wire dataa_w;
  59 wire datab_w;
  60 wire datac_w;
  61 wire datad_w;
  62 wire cin_w;
  63
  64 assign dataa_w = din0;
  65 assign datab_w = din1;
  66 assign datac_w = din2;
  67 assign datad_w = din3;
  68
  69 function lut_data;
  70 input [15:0] mask;
  71 input        dataa, datab, datac, datad;
  72 reg [7:0]   s3;
  73 reg [3:0]   s2;
  74 reg [1:0]   s1;
  75   begin
  76        s3 = datad ? mask[15:8] : mask[7:0];
  77        s2 = datac ?   s3[7:4]  :   s3[3:0];
  78        s1 = datab ?   s2[3:2]  :   s2[1:0];
  79        lut_data = dataa ? s1[1] : s1[0];
  80   end
  81
  82 endfunction
  83
  84 initial begin
  85     /*if (sum_lutc_input == "datac")*/ lut_type = 0;
  86     /*else
  87     if (sum_lutc_input == "cin")   lut_type = 1;
  88     else begin
  89       $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
  90       $finish();
  91     end*/
  92 end
  93
  94 always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
  95     if (lut_type == 0) begin // logic function
  96         combout_rt = lut_data(lut_function, dataa_w, datab_w,
  97                             datac_w, datad_w);
  98     end
  99     else if (lut_type == 1) begin // arithmetic function
 100         combout_rt = lut_data(lut_function, dataa_w, datab_w,
 101                             cin_w, datad_w);
 102     end
 103     cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0);
 104 end
 105
 106 assign dout = combout_rt & 1'b1;
 107 //assign cout = cout_rt & 1'b1;
 108
 109 endmodule // fiftyfivenm_lcell_comb
 110
 111 /* Altera MAX10 D Flip-Flop Primitive */
 112 // TODO: Implement advanced simulation functions
 113 module dffeas ( output q,
 114                 input d, clk, clrn, prn, ena,
 115                 input asdata, aload, sclr, sload );
 116
 117 parameter power_up="dontcare";
 118 parameter is_wysiwyg="false";
 119   reg q;
 120
 121   always @(posedge clk)
 122     q <= d;
 123
 124 endmodule
 125
 126
 127