techlibs/achronix/synth_achronix.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthAchronixPass : public ScriptPass {
  29   SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
  30
  31   void help() YS_OVERRIDE
  32   {
  33     //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  34     log("\n");
  35     log("    synth_achronix [options]\n");
  36     log("\n");
  37     log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
  38     log("\n");
  39     log("    -top <module>\n");
  40     log("        use the specified module as top module (default='top')\n");
  41     log("\n");
  42     log("    -vout <file>\n");
  43     log("        write the design to the specified Verilog netlist file. writing of an\n");
  44     log("        output file is omitted if this parameter is not specified.\n");
  45     log("\n");
  46     log("    -run <from_label>:<to_label>\n");
  47     log("        only run the commands between the labels (see below). an empty\n");
  48     log("        from label is synonymous to 'begin', and empty to label is\n");
  49     log("        synonymous to the end of the command list.\n");
  50     log("\n");
  51     log("    -noflatten\n");
  52     log("        do not flatten design before synthesis\n");
  53     log("\n");
  54     log("    -retime\n");
  55     log("        run 'abc' with '-dff -D 1' options\n");
  56     log("\n");
  57     log("\n");
  58     log("The following commands are executed by this synthesis command:\n");
  59     help_script();
  60     log("\n");
  61   }
  62
  63   string top_opt, family_opt, vout_file;
  64   bool retime, flatten;
  65
  66   void clear_flags() YS_OVERRIDE
  67   {
  68     top_opt = "-auto-top";
  69     vout_file = "";
  70     retime = false;
  71     flatten = true;
  72   }
  73
  74   void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  75   {
  76     string run_from, run_to;
  77     clear_flags();
  78
  79     size_t argidx;
  80     for (argidx = 1; argidx < args.size(); argidx++)
  81       {
  82         if (args[argidx] == "-top" && argidx+1 < args.size()) {
  83           top_opt = "-top " + args[++argidx];
  84           continue;
  85         }
  86         if (args[argidx] == "-vout" && argidx+1 < args.size()) {
  87           vout_file = args[++argidx];
  88           continue;
  89         }
  90         if (args[argidx] == "-run" && argidx+1 < args.size()) {
  91           size_t pos = args[argidx+1].find(':');
  92           if (pos == std::string::npos)
  93             break;
  94           run_from = args[++argidx].substr(0, pos);
  95           run_to = args[argidx].substr(pos+1);
  96           continue;
  97         }
  98         if (args[argidx] == "-noflatten") {
  99           flatten = false;
 100           continue;
 101         }
 102         if (args[argidx] == "-retime") {
 103           retime = true;
 104           continue;
 105         }
 106         break;
 107       }
 108     extra_args(args, argidx, design);
 109
 110     if (!design->full_selection())
 111       log_cmd_error("This command only operates on fully selected designs!\n");
 112
 113     log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
 114     log_push();
 115
 116     run_script(design, run_from, run_to);
 117
 118     log_pop();
 119   }
 120
 121   void script() YS_OVERRIDE
 122   {
 123     if (check_label("begin"))
 124       {
 125         run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
 126         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 127       }
 128
 129     if (flatten && check_label("flatten", "(unless -noflatten)"))
 130       {
 131         run("proc");
 132         run("flatten");
 133         run("tribuf -logic");
 134         run("deminout");
 135       }
 136
 137     if (check_label("coarse"))
 138       {
 139         run("synth -run coarse");
 140       }
 141
 142     if (check_label("fine"))
 143       {
 144         run("opt -fast -mux_undef -undriven -fine -full");
 145         run("memory_map");
 146         run("opt -undriven -fine");
 147         run("dff2dffe -direct-match $_DFF_*");
 148         run("opt -fine");
 149         run("techmap -map +/techmap.v");
 150         run("opt -full");
 151         run("clean -purge");
 152         run("setundef -undriven -zero");
 153         if (retime || help_mode)
 154           run("abc -markgroups -dff -D 1", "(only if -retime)");
 155       }
 156
 157     if (check_label("map_luts"))
 158       {
 159         run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
 160         run("clean");
 161       }
 162
 163     if (check_label("map_cells"))
 164       {
 165         run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
 166         run("techmap -map +/achronix/speedster22i/cells_map.v");
 167         // VT: not done yet run("dffinit -highlow -ff DFF q power_up");
 168         run("clean -purge");
 169       }
 170
 171     if (check_label("check"))
 172       {
 173         run("hierarchy -check");
 174         run("stat");
 175         run("check -noinit");
 176       }
 177
 178     if (check_label("vout"))
 179       {
 180         if (!vout_file.empty() || help_mode)
 181           run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
 182                       help_mode ? "<file-name>" : vout_file.c_str()));
 183       }
 184   }
 185 } SynthAchronixPass;
 186
 187 PRIVATE_NAMESPACE_END