92b10781d5abd8d71c0743402e07f2262f809e5c
2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthAchronixPass
: public ScriptPass
{
29 SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
31 void help() YS_OVERRIDE
33 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log(" synth_achronix [options]\n");
37 log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
39 log(" -top <module>\n");
40 log(" use the specified module as top module (default='top')\n");
42 log(" -vout <file>\n");
43 log(" write the design to the specified Verilog netlist file. writing of an\n");
44 log(" output file is omitted if this parameter is not specified.\n");
46 log(" -run <from_label>:<to_label>\n");
47 log(" only run the commands between the labels (see below). an empty\n");
48 log(" from label is synonymous to 'begin', and empty to label is\n");
49 log(" synonymous to the end of the command list.\n");
52 log(" do not flatten design before synthesis\n");
55 log(" run 'abc' with -dff option\n");
58 log("The following commands are executed by this synthesis command:\n");
63 string top_opt
, family_opt
, vout_file
;
66 void clear_flags() YS_OVERRIDE
68 top_opt
= "-auto-top";
74 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
76 string run_from
, run_to
;
80 for (argidx
= 1; argidx
< args
.size(); argidx
++)
82 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
83 top_opt
= "-top " + args
[++argidx
];
86 if (args
[argidx
] == "-vout" && argidx
+1 < args
.size()) {
87 vout_file
= args
[++argidx
];
90 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
91 size_t pos
= args
[argidx
+1].find(':');
92 if (pos
== std::string::npos
)
94 run_from
= args
[++argidx
].substr(0, pos
);
95 run_to
= args
[argidx
].substr(pos
+1);
98 if (args
[argidx
] == "-flatten") {
102 if (args
[argidx
] == "-retime") {
108 extra_args(args
, argidx
, design
);
110 if (!design
->full_selection())
111 log_cmd_error("This comannd only operates on fully selected designs!\n");
113 log_header(design
, "Executing SYNTH_ACHRONIX pass.\n");
116 run_script(design
, run_from
, run_to
);
121 void script() YS_OVERRIDE
123 if (check_label("begin"))
125 run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
126 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
129 if (flatten
&& check_label("flatten", "(unless -noflatten)"))
133 run("tribuf -logic");
137 if (check_label("coarse"))
139 run("synth -run coarse");
142 if (check_label("fine"))
144 run("opt -fast -mux_undef -undriven -fine -full");
146 run("opt -undriven -fine");
148 run("dff2dffe -direct-match $_DFF_*");
150 run("techmap -map +/techmap.v");
153 run("setundef -undriven -zero");
154 if (retime
|| help_mode
)
155 run("abc -markgroups -dff", "(only if -retime)");
158 if (check_label("map_luts"))
160 run("abc -lut 4" + string(retime
? " -dff" : ""));
164 if (check_label("map_cells"))
166 run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
167 run("techmap -map +/achronix/speedster22i/cells_map.v");
168 // VT: not done yet run("dffinit -highlow -ff DFF q power_up");
172 if (check_label("check"))
174 run("hierarchy -check");
176 run("check -noinit");
179 if (check_label("vout"))
181 if (!vout_file
.empty() || help_mode
)
182 run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
183 help_mode
? "<file-name>" : vout_file
.c_str()));
188 PRIVATE_NAMESPACE_END