abc9: generate $abc9_holes design instead of <name>$holes
[yosys.git] / techlibs / anlogic / Makefile.inc
1
2 OBJS += techlibs/anlogic/synth_anlogic.o
3 OBJS += techlibs/anlogic/anlogic_eqn.o
4 OBJS += techlibs/anlogic/anlogic_fixcarry.o
5
6 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
7 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
8 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
9 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
10 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
11 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
12 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))