2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct AnlogicDetermineInitPass
: public Pass
{
27 AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
28 void help() YS_OVERRIDE
31 log(" anlogic_determine_init [selection]\n");
33 log("Determine the init value of cells that doesn't allow unknown init value.\n");
37 Const
determine_init(Const init
)
39 for (int i
= 0; i
< GetSize(init
); i
++) {
40 if (init
[i
] != State::S0
&& init
[i
] != State::S1
)
47 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
49 log_header(design
, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
51 extra_args(args
, args
.size(), design
);
54 for (auto module
: design
->selected_modules())
56 for (auto cell
: module
->selected_cells())
58 if (cell
->type
== "\\EG_LOGIC_DRAM16X4")
60 cell
->setParam("\\INIT_D0", determine_init(cell
->getParam("\\INIT_D0")));
61 cell
->setParam("\\INIT_D1", determine_init(cell
->getParam("\\INIT_D1")));
62 cell
->setParam("\\INIT_D2", determine_init(cell
->getParam("\\INIT_D2")));
63 cell
->setParam("\\INIT_D3", determine_init(cell
->getParam("\\INIT_D3")));
68 log_header(design
, "Updated %lu cells with determined init value.\n", cnt
);
70 } AnlogicDetermineInitPass
;