2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
5 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 (* techmap_celltype = "$alu" *)
22 module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
23 parameter A_SIGNED = 0;
24 parameter B_SIGNED = 0;
25 parameter A_WIDTH = 1;
26 parameter B_WIDTH = 1;
27 parameter Y_WIDTH = 1;
29 input [A_WIDTH-1:0] A;
30 input [B_WIDTH-1:0] B;
31 output [Y_WIDTH-1:0] X, Y;
36 wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
38 wire [Y_WIDTH-1:0] A_buf, B_buf;
39 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
40 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
42 wire [Y_WIDTH-1:0] AA = A_buf;
43 wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
44 wire [Y_WIDTH+1:0] COx;
45 wire [Y_WIDTH+1:0] C = {COx, CI};
50 .ALUTYPE("ADD_CARRY"))
57 generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
58 if(i==Y_WIDTH-1) begin
66 assign CO = COx[Y_WIDTH];
82 /* End implementation */