techlibs/anlogic/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2018  Miodrag Milanovic <miodrag@symbioticeda.com>
   5  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 (* techmap_celltype = "$alu" *)
  22 module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
  23         parameter A_SIGNED = 0;
  24         parameter B_SIGNED = 0;
  25         parameter A_WIDTH  = 1;
  26         parameter B_WIDTH  = 1;
  27         parameter Y_WIDTH  = 1;
  28
  29         (* force_downto *)
  30         input [A_WIDTH-1:0] A;
  31         (* force_downto *)
  32         input [B_WIDTH-1:0] B;
  33         (* force_downto *)
  34         output [Y_WIDTH-1:0] X, Y;
  35
  36         input CI, BI;
  37         (* force_downto *)
  38         output [Y_WIDTH-1:0] CO;
  39
  40         wire CIx;
  41         (* force_downto *)
  42         wire [Y_WIDTH-1:0] COx;
  43
  44         wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
  45
  46         (* force_downto *)
  47         wire [Y_WIDTH-1:0] A_buf, B_buf;
  48         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
  49         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
  50
  51         (* force_downto *)
  52         wire [Y_WIDTH-1:0] AA = A_buf;
  53         (* force_downto *)
  54         wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
  55         (* force_downto *)
  56         wire [Y_WIDTH-1:0] C = { COx, CIx };
  57
  58     wire dummy;
  59     AL_MAP_ADDER #(
  60         .ALUTYPE("ADD_CARRY"))
  61     adder_cin  (
  62         .a(CI),
  63                 .b(1'b0),
  64                 .c(1'b0),
  65         .o({CIx, dummy})
  66         );
  67
  68         genvar i;
  69         generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
  70             AL_MAP_ADDER #(
  71             .ALUTYPE("ADD")
  72         ) adder_i (
  73             .a(AA[i]),
  74             .b(BB[i]),
  75             .c(C[i]),
  76             .o({COx[i],Y[i]})
  77         );
  78
  79                 wire cout;
  80                 AL_MAP_ADDER #(
  81                         .ALUTYPE("ADD"))
  82                 adder_cout  (
  83                         .a(1'b0),
  84                         .b(1'b0),
  85                         .c(COx[i]),
  86                         .o({cout, CO[i]})
  87                 );
  88           end: slice
  89         endgenerate
  90
  91    /* End implementation */
  92    assign X = AA ^ BB;
  93 endmodule