techlibs/anlogic/cells_sim.v

   1 module AL_MAP_SEQ (
   2         output reg q,
   3         input ce,
   4         input clk,
   5         input sr,
   6         input d
   7 );
   8         parameter DFFMODE = "FF"; //FF,LATCH
   9         parameter REGSET = "RESET"; //RESET/SET
  10         parameter SRMUX = "SR"; //SR/INV
  11         parameter SRMODE = "SYNC"; //SYNC/ASYNC
  12
  13         wire clk_ce;
  14         assign clk_ce = ce ? clk : 1'b0;
  15
  16         wire srmux;
  17         generate
  18                 case (SRMUX)
  19                         "SR": assign srmux = sr;
  20                         "INV": assign srmux = ~sr;
  21                         default: assign srmux = sr;
  22                 endcase
  23         endgenerate
  24
  25         wire regset;
  26         generate
  27                 case (REGSET)
  28                         "RESET": assign regset = 1'b0;
  29                         "SET": assign regset = 1'b1;
  30                         default: assign regset = 1'b0;
  31                 endcase
  32         endgenerate
  33
  34         initial q = regset;
  35
  36         generate
  37                 if (DFFMODE == "FF")
  38                 begin
  39                         if (SRMODE == "ASYNC")
  40                         begin
  41                                 always @(posedge clk_ce, posedge srmux)
  42                                         if (srmux)
  43                                                 q <= regset;
  44                                         else
  45                                                 q <= d;
  46                         end
  47                         else
  48                         begin
  49                                 always @(posedge clk_ce)
  50                                         if (srmux)
  51                                                 q <= regset;
  52                                         else
  53                                                 q <= d;
  54                         end
  55                 end
  56                 else
  57                 begin
  58                         // DFFMODE == "LATCH"
  59                         if (SRMODE == "ASYNC")
  60                         begin
  61                                 always @(clk_ce, srmux)
  62                                         if (srmux)
  63                                                 q <= regset;
  64                                         else
  65                                                 q <= d;
  66                         end
  67                         else
  68                         begin
  69                                 always @(clk_ce)
  70                                         if (srmux)
  71                                                 q <= regset;
  72                                         else
  73                                                 q <= d;
  74                         end
  75                 end
  76     endgenerate
  77 endmodule
  78
  79 module AL_MAP_LUT1 (
  80         output o,
  81         input a
  82 );
  83         parameter [1:0] INIT = 2'h0;
  84         parameter EQN = "(A)";
  85
  86         assign o = a ? INIT[1] : INIT[0];
  87 endmodule
  88
  89 module AL_MAP_LUT2 (
  90         output o,
  91         input a,
  92         input b
  93 );
  94         parameter [3:0] INIT = 4'h0;
  95         parameter EQN = "(A)";
  96
  97         wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
  98         assign o = a ? s1[1] : s1[0];
  99 endmodule
 100
 101 module AL_MAP_LUT3 (
 102         output o,
 103         input a,
 104         input b,
 105         input c
 106 );
 107         parameter [7:0] INIT = 8'h0;
 108         parameter EQN = "(A)";
 109
 110         wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
 111         wire [1:0] s1 = b ?   s2[ 3:2] :   s2[1:0];
 112         assign o = a ? s1[1] : s1[0];
 113 endmodule
 114
 115 module AL_MAP_LUT4 (
 116         output o,
 117         input a,
 118         input b,
 119         input c,
 120         input d
 121 );
 122         parameter [15:0] INIT = 16'h0;
 123         parameter EQN = "(A)";
 124
 125         wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
 126         wire [3:0] s2 = c ?   s3[ 7:4] :   s3[3:0];
 127         wire [1:0] s1 = b ?   s2[ 3:2] :   s2[1:0];
 128         assign o = a ? s1[1] : s1[0];
 129 endmodule
 130
 131 module AL_MAP_LUT5 (
 132         output o,
 133         input a,
 134         input b,
 135         input c,
 136         input d,
 137         input e
 138 );
 139         parameter [31:0] INIT = 32'h0;
 140         parameter EQN = "(A)";
 141         assign o = INIT >> {e, d, c, b, a};
 142 endmodule
 143
 144
 145 module AL_MAP_LUT6 (
 146         output o,
 147         input a,
 148         input b,
 149         input c,
 150         input d,
 151         input e,
 152         input f
 153 );
 154         parameter [63:0] INIT = 64'h0;
 155         parameter EQN = "(A)";
 156         assign o = INIT >> {f, e, d, c, b, a};
 157 endmodule
 158
 159 module AL_MAP_ALU2B (
 160    input cin,
 161    input a0, b0, c0, d0,
 162    input a1, b1, c1, d1,
 163    output s0, s1, cout
 164 );
 165         parameter [15:0] INIT0 = 16'h0000;
 166         parameter [15:0] INIT1 = 16'h0000;
 167         parameter FUNC0 = "NO";
 168         parameter FUNC1 = "NO";
 169 endmodule
 170
 171 module AL_MAP_ADDER (
 172   input a,
 173   input b,
 174   input c,
 175   output [1:0] o
 176 );
 177         parameter ALUTYPE = "ADD";
 178
 179         generate
 180                 case (ALUTYPE)
 181                         "ADD":           assign o = a + b + c;
 182                         "SUB":           assign o = a - b - c;
 183                         "A_LE_B":    assign o = a - b - c;
 184
 185                         "ADD_CARRY":    assign o = {  a, 1'b0 };
 186                         "SUB_CARRY":    assign o = { ~a, 1'b0 };
 187                         "A_LE_B_CARRY": assign o = {  a, 1'b0 };
 188                         default: assign o = a + b + c;
 189                 endcase
 190         endgenerate
 191
 192 endmodule