Merge pull request #871 from YosysHQ/verific_import
[yosys.git] / techlibs / anlogic / drams.txt
1 bram $__ANLOGIC_DRAM16X4
2 init 1
3 abits 4
4 dbits 4
5 groups 2
6 ports 1 1
7 wrmode 0 1
8 enable 0 1
9 transp 0 0
10 clocks 0 1
11 clkpol 0 1
12 endbram
13
14 match $__ANLOGIC_DRAM16X4
15 make_outreg
16 endmatch