techlibs/anlogic/drams_map.v

   1 module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
   2         parameter [63:0]INIT = 64'bx;
   3         input CLK1;
   4
   5         input [3:0] A1ADDR;
   6         output [3:0] A1DATA;
   7
   8         input [3:0] B1ADDR;
   9         input [3:0] B1DATA;
  10         input B1EN;
  11
  12         EG_LOGIC_DRAM16X4 #(
  13                 `include "dram_init_16x4.vh"
  14         ) _TECHMAP_REPLACE_ (
  15                 .di(B1DATA),
  16                 .waddr(B1ADDR),
  17                 .wclk(CLK1),
  18                 .we(B1EN),
  19                 .raddr(A1ADDR),
  20                 .do(A1DATA)
  21         );
  22 endmodule