projects
/
yosys.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
history
|
raw
|
HEAD
Merge pull request #746 from Icenowy/anlogic-dram
[yosys.git]
/
techlibs
/
anlogic
/
drams_map.v
1
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
2
input CLK1;
3
4
input [3:0] A1ADDR;
5
output [3:0] A1DATA;
6
7
input [3:0] B1ADDR;
8
input [3:0] B1DATA;
9
input B1EN;
10
11
EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
12
.di(B1DATA),
13
.waddr(B1ADDR),
14
.wclk(CLK1),
15
.we(B1EN),
16
.raddr(A1ADDR),
17
.do(A1DATA)
18
);
19
endmodule