2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
5 * Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
27 PRIVATE_NAMESPACE_BEGIN
29 struct SynthAnlogicPass
: public ScriptPass
31 SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { }
33 void help() YS_OVERRIDE
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
37 log(" synth_anlogic [options]\n");
39 log("This command runs synthesis for Anlogic FPGAs.\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
44 log(" -edif <file>\n");
45 log(" write the design to the specified EDIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
48 log(" -json <file>\n");
49 log(" write the design to the specified JSON file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
52 log(" -run <from_label>:<to_label>\n");
53 log(" only run the commands between the labels (see below). an empty\n");
54 log(" from label is synonymous to 'begin', and empty to label is\n");
55 log(" synonymous to the end of the command list.\n");
58 log(" do not flatten design before synthesis\n");
61 log(" run 'abc' with -dff option\n");
64 log("The following commands are executed by this synthesis command:\n");
69 string top_opt
, edif_file
, json_file
;
72 void clear_flags() YS_OVERRIDE
74 top_opt
= "-auto-top";
81 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
83 string run_from
, run_to
;
87 for (argidx
= 1; argidx
< args
.size(); argidx
++)
89 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
90 top_opt
= "-top " + args
[++argidx
];
93 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
94 edif_file
= args
[++argidx
];
97 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
98 json_file
= args
[++argidx
];
101 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
102 size_t pos
= args
[argidx
+1].find(':');
103 if (pos
== std::string::npos
)
105 run_from
= args
[++argidx
].substr(0, pos
);
106 run_to
= args
[argidx
].substr(pos
+1);
109 if (args
[argidx
] == "-noflatten") {
113 if (args
[argidx
] == "-retime") {
119 extra_args(args
, argidx
, design
);
121 if (!design
->full_selection())
122 log_cmd_error("This command only operates on fully selected designs!\n");
124 log_header(design
, "Executing SYNTH_ANLOGIC pass.\n");
127 run_script(design
, run_from
, run_to
);
132 void script() YS_OVERRIDE
134 if (check_label("begin"))
136 run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
137 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
140 if (flatten
&& check_label("flatten", "(unless -noflatten)"))
144 run("tribuf -logic");
148 if (check_label("coarse"))
150 run("synth -run coarse");
153 if (check_label("dram"))
155 run("memory_bram -rules +/anlogic/drams.txt");
156 run("techmap -map +/anlogic/drams_map.v");
157 run("anlogic_determine_init");
160 if (check_label("fine"))
162 run("opt -fast -mux_undef -undriven -fine");
164 run("opt -undriven -fine");
165 run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
166 if (retime
|| help_mode
)
167 run("abc -dff", "(only if -retime)");
170 if (check_label("map_ffs"))
173 run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
174 run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
175 run("opt_expr -mux_undef");
179 if (check_label("map_luts"))
185 if (check_label("map_cells"))
187 run("techmap -map +/anlogic/cells_map.v");
192 if (check_label("check"))
194 run("hierarchy -check");
196 run("check -noinit");
199 if (check_label("edif"))
201 if (!edif_file
.empty() || help_mode
)
202 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
205 if (check_label("json"))
207 if (!json_file
.empty() || help_mode
)
208 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
213 PRIVATE_NAMESPACE_END