techlibs/cmos/counter.v

   1 module counter (clk, rst, en, count);
   2
   3    input clk, rst, en;
   4    output reg [3:0] count;
   5
   6    always @(posedge clk)
   7       if (rst)
   8          count <= 4'd0;
   9       else if (en)
  10          count <= count + 4'd1;
  11
  12 endmodule