techlibs/cmos/testbench.sp

   1
   2 * supply voltages
   3 .global Vss Vdd
   4 Vss Vss 0 DC 0
   5 Vdd Vdd 0 DC 3
   6
   7 * simple transistor model
   8 .MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
   9 .MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
  10
  11 * load design and library
  12 .include synth.sp
  13 .include cmos_cells.sp
  14
  15 * input signals
  16 Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
  17 Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
  18 Ven  en  0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
  19
  20 Xuut clk rst en out0 out1 out2 COUNTER
  21
  22 .tran 0.01 50
  23
  24 .control
  25 run
  26 plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
  27 .endc
  28
  29 .end