Hook up $aldff support in various passes.
[yosys.git] / techlibs / common / adff2dff.v
1 (* techmap_celltype = "$adff" *)
2 module adff2dff (CLK, ARST, D, Q);
3 parameter WIDTH = 1;
4 parameter CLK_POLARITY = 1;
5 parameter ARST_POLARITY = 1;
6 parameter ARST_VALUE = 0;
7
8 input CLK, ARST;
9 (* force_downto *)
10 input [WIDTH-1:0] D;
11 (* force_downto *)
12 output reg [WIDTH-1:0] Q;
13 (* force_downto *)
14 reg [WIDTH-1:0] NEXT_Q;
15
16 wire [1023:0] _TECHMAP_DO_ = "proc;;";
17
18 always @*
19 if (ARST == ARST_POLARITY)
20 NEXT_Q <= ARST_VALUE;
21 else
22 NEXT_Q <= D;
23
24 if (CLK_POLARITY)
25 always @(posedge CLK)
26 Q <= NEXT_Q;
27 else
28 always @(negedge CLK)
29 Q <= NEXT_Q;
30 endmodule