Try new LUT delays
[yosys.git] / techlibs / common / adff2dff.v
1 (* techmap_celltype = "$adff" *)
2 module adff2dff (CLK, ARST, D, Q);
3 parameter WIDTH = 1;
4 parameter CLK_POLARITY = 1;
5 parameter ARST_POLARITY = 1;
6 parameter ARST_VALUE = 0;
7
8 input CLK, ARST;
9 input [WIDTH-1:0] D;
10 output reg [WIDTH-1:0] Q;
11 wire reg [WIDTH-1:0] NEXT_Q;
12
13 wire [1023:0] _TECHMAP_DO_ = "proc;;";
14
15 always @*
16 if (ARST == ARST_POLARITY)
17 NEXT_Q <= ARST_VALUE;
18 else
19 NEXT_Q <= D;
20
21 if (CLK_POLARITY)
22 always @(posedge CLK)
23 Q <= NEXT_Q;
24 else
25 always @(negedge CLK)
26 Q <= NEXT_Q;
27 endmodule