Try new LUT delays
[yosys.git] / techlibs / common / dff2ff.v
1 (* techmap_celltype = "$dff" *)
2 module dff2ff (CLK, D, Q);
3 parameter WIDTH = 1;
4 parameter CLK_POLARITY = 1;
5
6 input CLK;
7 input [WIDTH-1:0] D;
8 output reg [WIDTH-1:0] Q;
9
10 wire [1023:0] _TECHMAP_DO_ = "proc;;";
11
12 always @($global_clock)
13 Q <= D;
14 endmodule