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Merge branch 'master' of github.com:YosysHQ/yosys
[yosys.git] / techlibs / common / mul2dsp.v
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 * 2019 David Shah <dave@ds0.me>
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 * ---
21 *
22 * Tech-mapping rules for decomposing arbitrarily-sized $mul cells
23 * into an equivalent collection of smaller `DSP_NAME cells (with the
24 * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
25 * to $shl and $add cells.
26 *
27 */
28
29 `ifndef DSP_A_MAXWIDTH
30 $fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
31 `endif
32 `ifndef DSP_B_MAXWIDTH
33 $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
34 `endif
35 `ifndef DSP_B_MAXWIDTH
36 $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
37 `endif
38 `ifndef DSP_A_MAXWIDTH_PARTIAL
39 `define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
40 `endif
41 `ifndef DSP_B_MAXWIDTH_PARTIAL
42 `define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
43 `endif
44
45 `ifndef DSP_NAME
46 $fatal(1, "Macro DSP_NAME must be defined");
47 `endif
48
49 `define MAX(a,b) (a > b ? a : b)
50 `define MIN(a,b) (a < b ? a : b)
51
52 (* techmap_celltype = "$mul $__mul" *)
53 module _80_mul (A, B, Y);
54 parameter A_SIGNED = 0;
55 parameter B_SIGNED = 0;
56 parameter A_WIDTH = 1;
57 parameter B_WIDTH = 1;
58 parameter Y_WIDTH = 1;
59
60 input [A_WIDTH-1:0] A;
61 input [B_WIDTH-1:0] B;
62 output [Y_WIDTH-1:0] Y;
63
64 parameter _TECHMAP_CELLTYPE_ = "";
65
66 generate
67 if (0) begin end
68 `ifdef DSP_A_MINWIDTH
69 else if (A_WIDTH < `DSP_A_MINWIDTH)
70 wire _TECHMAP_FAIL_ = 1;
71 `endif
72 `ifdef DSP_B_MINWIDTH
73 else if (B_WIDTH < `DSP_B_MINWIDTH)
74 wire _TECHMAP_FAIL_ = 1;
75 `endif
76 `ifdef DSP_Y_MINWIDTH
77 else if (Y_WIDTH < `DSP_Y_MINWIDTH)
78 wire _TECHMAP_FAIL_ = 1;
79 `endif
80 `ifdef DSP_SIGNEDONLY
81 else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
82 \$mul #(
83 .A_SIGNED(1),
84 .B_SIGNED(1),
85 .A_WIDTH(A_WIDTH + 1),
86 .B_WIDTH(B_WIDTH + 1),
87 .Y_WIDTH(Y_WIDTH)
88 ) _TECHMAP_REPLACE_ (
89 .A({1'b0, A}),
90 .B({1'b0, B}),
91 .Y(Y)
92 );
93 `endif
94 else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
95 \$mul #(
96 .A_SIGNED(B_SIGNED),
97 .B_SIGNED(A_SIGNED),
98 .A_WIDTH(B_WIDTH),
99 .B_WIDTH(A_WIDTH),
100 .Y_WIDTH(Y_WIDTH)
101 ) _TECHMAP_REPLACE_ (
102 .A(B),
103 .B(A),
104 .Y(Y)
105 );
106 else begin
107 wire [1023:0] _TECHMAP_DO_ = "proc; clean";
108
109 `ifdef DSP_SIGNEDONLY
110 localparam sign_headroom = 1;
111 `else
112 localparam sign_headroom = 0;
113 `endif
114
115 genvar i;
116 if (A_WIDTH > `DSP_A_MAXWIDTH) begin
117 localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
118 localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
119 localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
120 localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
121 if (A_SIGNED && B_SIGNED) begin
122 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
123 wire signed [last_Y_WIDTH-1:0] last_partial;
124 wire signed [Y_WIDTH-1:0] partial_sum [n:0];
125 end
126 else begin
127 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
128 wire [last_Y_WIDTH-1:0] last_partial;
129 wire [Y_WIDTH-1:0] partial_sum [n:0];
130 end
131
132 for (i = 0; i < n; i=i+1) begin:sliceA
133 \$__mul #(
134 .A_SIGNED(sign_headroom),
135 .B_SIGNED(B_SIGNED),
136 .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
137 .B_WIDTH(B_WIDTH),
138 .Y_WIDTH(partial_Y_WIDTH)
139 ) mul (
140 .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
141 .B(B),
142 .Y(partial[i])
143 );
144 // TODO: Currently a 'cascade' approach to summing the partial
145 // products is taken here, but a more efficient 'binary
146 // reduction' approach also exists...
147 if (i == 0)
148 assign partial_sum[i] = partial[i];
149 else
150 assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
151 end
152
153 \$__mul #(
154 .A_SIGNED(A_SIGNED),
155 .B_SIGNED(B_SIGNED),
156 .A_WIDTH(last_A_WIDTH),
157 .B_WIDTH(B_WIDTH),
158 .Y_WIDTH(last_Y_WIDTH)
159 ) sliceA.last (
160 .A(A[A_WIDTH-1 -: last_A_WIDTH]),
161 .B(B),
162 .Y(last_partial)
163 );
164 assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
165 assign Y = partial_sum[n];
166 end
167 else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
168 localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
169 localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
170 localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
171 localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
172 if (A_SIGNED && B_SIGNED) begin
173 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
174 wire signed [last_Y_WIDTH-1:0] last_partial;
175 wire signed [Y_WIDTH-1:0] partial_sum [n:0];
176 end
177 else begin
178 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
179 wire [last_Y_WIDTH-1:0] last_partial;
180 wire [Y_WIDTH-1:0] partial_sum [n:0];
181 end
182
183 for (i = 0; i < n; i=i+1) begin:sliceB
184 \$__mul #(
185 .A_SIGNED(A_SIGNED),
186 .B_SIGNED(sign_headroom),
187 .A_WIDTH(A_WIDTH),
188 .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
189 .Y_WIDTH(partial_Y_WIDTH)
190 ) mul (
191 .A(A),
192 .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
193 .Y(partial[i])
194 );
195 // TODO: Currently a 'cascade' approach to summing the partial
196 // products is taken here, but a more efficient 'binary
197 // reduction' approach also exists...
198 if (i == 0)
199 assign partial_sum[i] = partial[i];
200 else
201 assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
202 end
203
204 \$__mul #(
205 .A_SIGNED(A_SIGNED),
206 .B_SIGNED(B_SIGNED),
207 .A_WIDTH(A_WIDTH),
208 .B_WIDTH(last_B_WIDTH),
209 .Y_WIDTH(last_Y_WIDTH)
210 ) mul_sliceB_last (
211 .A(A),
212 .B(B[B_WIDTH-1 -: last_B_WIDTH]),
213 .Y(last_partial)
214 );
215 assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
216 assign Y = partial_sum[n];
217 end
218 else begin
219 if (A_SIGNED)
220 wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
221 else
222 wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
223 if (B_SIGNED)
224 wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
225 else
226 wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
227
228 `DSP_NAME #(
229 .A_SIGNED(A_SIGNED),
230 .B_SIGNED(B_SIGNED),
231 .A_WIDTH(`DSP_A_MAXWIDTH),
232 .B_WIDTH(`DSP_B_MAXWIDTH),
233 .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
234 ) _TECHMAP_REPLACE_ (
235 .A(Aext),
236 .B(Bext),
237 .Y(Y)
238 );
239 end
240 end
241 endgenerate
242 endmodule
243
244 (* techmap_celltype = "$mul $__mul" *)
245 module _90_soft_mul (A, B, Y);
246 parameter A_SIGNED = 0;
247 parameter B_SIGNED = 0;
248 parameter A_WIDTH = 1;
249 parameter B_WIDTH = 1;
250 parameter Y_WIDTH = 1;
251
252 input [A_WIDTH-1:0] A;
253 input [B_WIDTH-1:0] B;
254 output [Y_WIDTH-1:0] Y;
255
256 // Indirection necessary since mapping
257 // back to $mul will cause recursion
258 generate
259 if (A_SIGNED && !B_SIGNED)
260 \$__soft_mul #(
261 .A_SIGNED(A_SIGNED),
262 .B_SIGNED(1),
263 .A_WIDTH(A_WIDTH),
264 .B_WIDTH(B_WIDTH+1),
265 .Y_WIDTH(Y_WIDTH)
266 ) _TECHMAP_REPLACE_ (
267 .A(A),
268 .B({1'b0,B}),
269 .Y(Y)
270 );
271 else if (!A_SIGNED && B_SIGNED)
272 \$__soft_mul #(
273 .A_SIGNED(1),
274 .B_SIGNED(B_SIGNED),
275 .A_WIDTH(A_WIDTH+1),
276 .B_WIDTH(B_WIDTH),
277 .Y_WIDTH(Y_WIDTH)
278 ) _TECHMAP_REPLACE_ (
279 .A({1'b0,A}),
280 .B(B),
281 .Y(Y)
282 );
283 else
284 \$__soft_mul #(
285 .A_SIGNED(A_SIGNED),
286 .B_SIGNED(B_SIGNED),
287 .A_WIDTH(A_WIDTH),
288 .B_WIDTH(B_WIDTH),
289 .Y_WIDTH(Y_WIDTH)
290 ) _TECHMAP_REPLACE_ (
291 .A(A),
292 .B(B),
293 .Y(Y)
294 );
295 endgenerate
296 endmodule