techlibs/common/mul2dsp.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *                2019  David Shah    <dave@ds0.me>
   7  *
   8  *  Permission to use, copy, modify, and/or distribute this software for any
   9  *  purpose with or without fee is hereby granted, provided that the above
  10  *  copyright notice and this permission notice appear in all copies.
  11  *
  12  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  *  ---
  21  *
  22  *  Tech-mapping rules for decomposing arbitrarily-sized $mul cells
  23  *  into an equivalent collection of smaller `DSP_NAME cells (with the
  24  *  same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
  25  *  to $shl and $add cells.
  26  *
  27  */
  28
  29 `ifndef DSP_A_MAXWIDTH
  30 $error("Macro DSP_A_MAXWIDTH must be defined");
  31 `endif
  32 `ifndef DSP_B_MAXWIDTH
  33 $error("Macro DSP_B_MAXWIDTH must be defined");
  34 `endif
  35
  36 `ifndef DSP_NAME
  37 $error("Macro DSP_NAME must be defined");
  38 `endif
  39
  40 `define MAX(a,b) (a > b ? a : b)
  41 `define MIN(a,b) (a < b ? a : b)
  42
  43 module \$mul (A, B, Y);
  44         parameter A_SIGNED = 0;
  45         parameter B_SIGNED = 0;
  46         parameter A_WIDTH = 1;
  47         parameter B_WIDTH = 1;
  48         parameter Y_WIDTH = 1;
  49
  50         input [A_WIDTH-1:0] A;
  51         input [B_WIDTH-1:0] B;
  52         output [Y_WIDTH-1:0] Y;
  53
  54         generate
  55         if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
  56                 wire _TECHMAP_FAIL_ = 1;
  57         // NB: A_SIGNED == B_SIGNED == 0 from here
  58         else if (A_WIDTH >= B_WIDTH)
  59                 \$__mul #(
  60                         .A_SIGNED(A_SIGNED),
  61                         .B_SIGNED(B_SIGNED),
  62                         .A_WIDTH(A_WIDTH),
  63                         .B_WIDTH(B_WIDTH),
  64                         .Y_WIDTH(Y_WIDTH)
  65                 ) _TECHMAP_REPLACE_ (
  66                         .A(A),
  67                         .B(B),
  68                         .Y(Y)
  69                 );
  70         else
  71                 \$__mul #(
  72                         .A_SIGNED(B_SIGNED),
  73                         .B_SIGNED(A_SIGNED),
  74                         .A_WIDTH(B_WIDTH),
  75                         .B_WIDTH(A_WIDTH),
  76                         .Y_WIDTH(Y_WIDTH)
  77                 ) _TECHMAP_REPLACE_ (
  78                         .A(B),
  79                         .B(A),
  80                         .Y(Y)
  81                 );
  82         endgenerate
  83 endmodule
  84
  85 module \$__mul (A, B, Y);
  86         parameter A_SIGNED = 0;
  87         parameter B_SIGNED = 0;
  88         parameter A_WIDTH = 1;
  89         parameter B_WIDTH = 1;
  90         parameter Y_WIDTH = 1;
  91
  92         input [A_WIDTH-1:0] A;
  93         input [B_WIDTH-1:0] B;
  94         output [Y_WIDTH-1:0] Y;
  95
  96         wire [1023:0] _TECHMAP_DO_ = "proc; clean";
  97
  98 `ifdef DSP_SIGNEDONLY
  99         localparam sign_headroom = 1;
 100 `else
 101         localparam sign_headroom = 0;
 102 `endif
 103
 104         genvar i;
 105         generate
 106                 if (A_WIDTH <= 1 || B_WIDTH <= 1)
 107                         wire _TECHMAP_FAIL_ = 1;
 108 `ifdef DSP_MINWIDTH
 109                 else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH)
 110                         wire _TECHMAP_FAIL_ = 1;
 111 `endif
 112                 else if (A_WIDTH > `DSP_A_MAXWIDTH) begin
 113                         localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);
 114                         localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
 115                         localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom));
 116                         if (A_SIGNED && B_SIGNED) begin
 117                                 wire signed [partial_Y_WIDTH-1:0] partial [n-2:0];
 118                                 wire signed [last_Y_WIDTH-1:0] last_partial;
 119                                 wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
 120                         end
 121                         else begin
 122                                 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
 123                                 wire [last_Y_WIDTH-1:0] last_partial;
 124                                 wire [Y_WIDTH-1:0] partial_sum [n-1:0];
 125                         end
 126
 127                         \$__mul #(
 128                                 .A_SIGNED(sign_headroom),
 129                                 .B_SIGNED(B_SIGNED),
 130                                 .A_WIDTH(`DSP_A_MAXWIDTH),
 131                                 .B_WIDTH(B_WIDTH),
 132                                 .Y_WIDTH(partial_Y_WIDTH)
 133                         ) mul_slice_first (
 134                                 .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}),
 135                                 .B(B),
 136                                 .Y(partial[0])
 137                         );
 138                         assign partial_sum[0] = partial[0];
 139
 140                         for (i = 1; i < n-1; i=i+1) begin:slice
 141                                 \$__mul #(
 142                                         .A_SIGNED(sign_headroom),
 143                                         .B_SIGNED(B_SIGNED),
 144                                         .A_WIDTH(`DSP_A_MAXWIDTH),
 145                                         .B_WIDTH(B_WIDTH),
 146                                         .Y_WIDTH(partial_Y_WIDTH)
 147                                 ) mul_slice (
 148                                         .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}),
 149                                         .B(B),
 150                                         .Y(partial[i])
 151                                 );
 152                                 // TODO: Currently a 'cascade' approach to summing the partial
 153                                 //       products is taken here, but a more efficient 'binary
 154                                 //       reduction' approach also exists...
 155                                 assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
 156                         end
 157
 158                         \$__mul #(
 159                                 .A_SIGNED(A_SIGNED),
 160                                 .B_SIGNED(B_SIGNED),
 161                                 .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)),
 162                                 .B_WIDTH(B_WIDTH),
 163                                 .Y_WIDTH(last_Y_WIDTH)
 164                         ) mul_slice_last (
 165                                 .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]),
 166                                 .B(B),
 167                                 .Y(last_partial)
 168                         );
 169                         assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
 170                         assign Y = partial_sum[n-1];
 171                 end
 172                 else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
 173                         localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom);
 174                         localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);
 175                         localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom));
 176                         if (A_SIGNED && B_SIGNED) begin
 177                                 wire signed [partial_Y_WIDTH-1:0] partial [n-2:0];
 178                                 wire signed [last_Y_WIDTH-1:0] last_partial;
 179                                 wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
 180                         end
 181                         else begin
 182                                 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
 183                                 wire [last_Y_WIDTH-1:0] last_partial;
 184                                 wire [Y_WIDTH-1:0] partial_sum [n-1:0];
 185                         end
 186
 187                         \$__mul #(
 188                                 .A_SIGNED(A_SIGNED),
 189                                 .B_SIGNED(sign_headroom),
 190                                 .A_WIDTH(A_WIDTH),
 191                                 .B_WIDTH(`DSP_B_MAXWIDTH),
 192                                 .Y_WIDTH(partial_Y_WIDTH)
 193                         ) mul_first (
 194                                 .A(A),
 195                                 .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}),
 196                                 .Y(partial[0])
 197                         );
 198                         assign partial_sum[0] = partial[0];
 199
 200                         for (i = 1; i < n-1; i=i+1) begin:slice
 201                                 \$__mul #(
 202                                         .A_SIGNED(A_SIGNED),
 203                                         .B_SIGNED(sign_headroom),
 204                                         .A_WIDTH(A_WIDTH),
 205                                         .B_WIDTH(`DSP_B_MAXWIDTH),
 206                                         .Y_WIDTH(partial_Y_WIDTH)
 207                                 ) mul (
 208                                         .A(A),
 209                                         .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}),
 210                                         .Y(partial[i])
 211                                 );
 212                 // TODO: Currently a 'cascade' approach to summing the partial
 213                 //       products is taken here, but a more efficient 'binary
 214                 //       reduction' approach also exists...
 215                                 assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
 216                         end
 217
 218                         \$__mul #(
 219                                 .A_SIGNED(A_SIGNED),
 220                                 .B_SIGNED(B_SIGNED),
 221                                 .A_WIDTH(A_WIDTH),
 222                                 .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)),
 223                                 .Y_WIDTH(last_Y_WIDTH)
 224                         ) mul_last (
 225                                 .A(A),
 226                                 .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
 227                                 .Y(last_partial)
 228                         );
 229                         assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
 230                         assign Y = partial_sum[n-1];
 231                 end
 232                 else begin
 233                         `DSP_NAME #(
 234                                 .A_SIGNED(A_SIGNED),
 235                                 .B_SIGNED(B_SIGNED),
 236                                 .A_WIDTH(A_WIDTH),
 237                                 .B_WIDTH(B_WIDTH),
 238                                 .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)),
 239                         ) _TECHMAP_REPLACE_ (
 240                                 .A(A),
 241                                 .B(B),
 242                                 .Y(Y)
 243                         );
 244                 end
 245         endgenerate
 246 endmodule
 247
 248 (* techmap_celltype = "$__mul" *)
 249 module $__soft_mul (A, B, Y);
 250         parameter A_SIGNED = 0;
 251         parameter B_SIGNED = 0;
 252         parameter A_WIDTH = 1;
 253         parameter B_WIDTH = 1;
 254         parameter Y_WIDTH = 1;
 255
 256         input [A_WIDTH-1:0] A;
 257         input [B_WIDTH-1:0] B;
 258         output [Y_WIDTH-1:0] Y;
 259
 260         // Indirection necessary since mapping
 261         //   back to $mul will cause recursion
 262         generate
 263                 if (A_SIGNED && !B_SIGNED)
 264                         \$__soft__mul #(
 265                                 .A_SIGNED(A_SIGNED),
 266                                 .B_SIGNED(1),
 267                                 .A_WIDTH(A_WIDTH),
 268                                 .B_WIDTH(B_WIDTH+1),
 269                                 .Y_WIDTH(Y_WIDTH)
 270                         ) _TECHMAP_REPLACE_ (
 271                                 .A(A),
 272                                 .B({1'b0,B}),
 273                                 .Y(Y)
 274                         );
 275                 else if (!A_SIGNED && B_SIGNED)
 276                         \$__soft_mul #(
 277                                 .A_SIGNED(1),
 278                                 .B_SIGNED(B_SIGNED),
 279                                 .A_WIDTH(A_WIDTH+1),
 280                                 .B_WIDTH(B_WIDTH),
 281                                 .Y_WIDTH(Y_WIDTH)
 282                         ) _TECHMAP_REPLACE_ (
 283                                 .A({1'b0,A}),
 284                                 .B(B),
 285                                 .Y(Y)
 286                         );
 287                 else
 288                         \$__soft_mul #(
 289                                 .A_SIGNED(A_SIGNED),
 290                                 .B_SIGNED(B_SIGNED),
 291                                 .A_WIDTH(A_WIDTH),
 292                                 .B_WIDTH(B_WIDTH),
 293                                 .Y_WIDTH(Y_WIDTH)
 294                         ) _TECHMAP_REPLACE_ (
 295                                 .A(A),
 296                                 .B(B),
 297                                 .Y(Y)
 298                         );
 299         endgenerate
 300 endmodule